diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/abc/abc.cc | 10 | ||||
| -rw-r--r-- | passes/opt/opt_clean.cc | 4 |
2 files changed, 9 insertions, 5 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 1a7de066..3e105411 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -59,6 +59,7 @@ PRIVATE_NAMESPACE_BEGIN enum class gate_type_t { G_NONE, G_FF, + G_BUF, G_NOT, G_AND, G_NAND, @@ -160,7 +161,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) return; } - if (cell->type == "$_NOT_") + if (cell->type.in("$_BUF_", "$_NOT_")) { RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_y = cell->getPort("\\Y"); @@ -168,7 +169,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) assign_map.apply(sig_a); assign_map.apply(sig_y); - map_signal(sig_y, G(NOT), map_signal(sig_a)); + map_signal(sig_y, cell->type == "$_BUF_" ? G(BUF) : G(NOT), map_signal(sig_a)); module->remove(cell); return; @@ -645,7 +646,10 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std int count_gates = 0; for (auto &si : signal_list) { - if (si.type == G(NOT)) { + if (si.type == G(BUF)) { + fprintf(f, ".names n%d n%d\n", si.in1, si.id); + fprintf(f, "1 1\n"); + } else if (si.type == G(NOT)) { fprintf(f, ".names n%d n%d\n", si.in1, si.id); fprintf(f, "0 1\n"); } else if (si.type == G(AND)) { diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 15bbf54e..004a2078 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -295,8 +295,8 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose) std::vector<RTLIL::Cell*> delcells; for (auto cell : module->cells()) - if (cell->type == "$pos") { - bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); + if (cell->type.in("$pos", "$_BUF_")) { + bool is_signed = cell->type == "$pos" && cell->getParam("\\A_SIGNED").as_bool(); RTLIL::SigSpec a = cell->getPort("\\A"); RTLIL::SigSpec y = cell->getPort("\\Y"); a.extend_u0(SIZE(y), is_signed); |