diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/techmap.cc | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index f0d1e6da..53164b58 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -151,18 +151,18 @@ struct TechmapWorker if (c.second.width < c.first.width) c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.width - c.second.width)); assert(c.first.width == c.second.width); -#if 0 - // more conservative approach: - // connect internal and external wires - module->connections.push_back(c); -#else - // approach that yields nicer outputs: - // replace internal wires that are connected to external wires - if (w->port_output) - port_signal_map.add(c.second, c.first); - else - port_signal_map.add(c.first, c.second); -#endif + if (flatten_mode) { + // more conservative approach: + // connect internal and external wires + module->connections.push_back(c); + } else { + // approach that yields nicer outputs: + // replace internal wires that are connected to external wires + if (w->port_output) + port_signal_map.add(c.second, c.first); + else + port_signal_map.add(c.first, c.second); + } } for (auto &it : tpl->cells) { |