diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/select.cc | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 137f8618..5712a023 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -272,6 +272,21 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v if (lhs.selected_member(mod_it.first, it.first) && limits.count(it.first) == 0) selected_wires.insert(it.second); + for (auto &conn : mod->connections) + { + std::vector<RTLIL::SigBit> conn_lhs = conn.first.to_sigbit_vector(); + std::vector<RTLIL::SigBit> conn_rhs = conn.second.to_sigbit_vector(); + + for (size_t i = 0; i < conn_lhs.size(); i++) { + if (conn_lhs[i].wire == NULL || conn_rhs[i].wire == NULL) + continue; + if (mode != 'i' && selected_wires.count(conn_rhs[i].wire) && lhs.selected_members[mod->name].count(conn_lhs[i].wire->name) == 0) + lhs.selected_members[mod->name].insert(conn_lhs[i].wire->name), sel_objects++, max_objects--; + if (mode != 'o' && selected_wires.count(conn_lhs[i].wire) && lhs.selected_members[mod->name].count(conn_rhs[i].wire->name) == 0) + lhs.selected_members[mod->name].insert(conn_rhs[i].wire->name), sel_objects++, max_objects--; + } + } + for (auto &cell : mod->cells) for (auto &conn : cell.second->connections) { |