Diffstat (limited to 'techlibs/common/simcells.v')
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index d492c2f1..7c8a47dd 100644
@@ -20,12 +20,12 @@
* The internal logic cell simulation library.
* This verilog library contains simple simulation models for the internal
- * logic cells ($_INV_ , $_AND_ , ...) that are generated by the default technology
+ * logic cells ($_NOT_ , $_AND_ , ...) that are generated by the default technology
* mapper (see "techmap.v" in this directory) and expected by the "abc" pass.
-module \$_INV_ (A, Y);
+module \$_NOT_ (A, Y);
assign Y = ~A;