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-rw-r--r--techlibs/common/simlib.v15
1 files changed, 15 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 0e041e12..8f354a63 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -733,6 +733,21 @@ endmodule
// --------------------------------------------------------
+module \$assert (A, EN);
+
+input A, EN;
+
+always @* begin
+ if (A !== 1'b1 && EN === 1'b1) begin
+ $display("Assertation failed!");
+ $finish;
+ end
+end
+
+endmodule
+
+// --------------------------------------------------------
+
module \$sr (SET, CLR, Q);
parameter WIDTH = 0;