summaryrefslogtreecommitdiff
path: root/techlibs/common/simlib.v
diff options
context:
space:
mode:
Diffstat (limited to 'techlibs/common/simlib.v')
-rw-r--r--techlibs/common/simlib.v32
1 files changed, 32 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 4436abfe..908314f8 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1097,6 +1097,38 @@ endmodule
// --------------------------------------------------------
+module \$dlatchsr (EN, SET, CLR, D, Q);
+
+parameter WIDTH = 0;
+parameter EN_POLARITY = 1'b1;
+parameter SET_POLARITY = 1'b1;
+parameter CLR_POLARITY = 1'b1;
+
+input EN;
+input [WIDTH-1:0] SET, CLR, D;
+output reg [WIDTH-1:0] Q;
+
+wire pos_en = EN == EN_POLARITY;
+wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
+wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
+
+genvar i;
+generate
+ for (i = 0; i < WIDTH; i = i+1) begin:bit
+ always @*
+ if (pos_clr[i])
+ Q[i] <= 0;
+ else if (pos_set[i])
+ Q[i] <= 1;
+ else if (pos_en)
+ Q[i] <= D[i];
+ end
+endgenerate
+
+endmodule
+
+// --------------------------------------------------------
+
module \$fsm (CLK, ARST, CTRL_IN, CTRL_OUT);
parameter NAME = "";