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-rw-r--r--techlibs/common/simlib.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index da745b5e..dd12bd39 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -453,7 +453,7 @@ output [WIDTH-1:0] X, Y;
wire [WIDTH-1:0] t1, t2, t3;
assign t1 = A ^ B, t2 = A & B, t3 = C & t1;
-assign Y = t1 ^ C, X = t2 | t3;
+assign Y = t1 ^ C, X = (t2 | t3) ^ (Y ^ Y);
endmodule