diff options
Diffstat (limited to 'techlibs/common/synth.cc')
| -rw-r--r-- | techlibs/common/synth.cc | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index a50db53e..56ab6eaf 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -90,12 +90,14 @@ struct SynthPass : public Pass { log(" techmap\n"); log(" opt -fast\n"); #ifdef YOSYS_ENABLE_ABC - log("\n"); - log(" abc:\n"); log(" abc -fast\n"); log(" opt -fast\n"); #endif log("\n"); + log(" check:\n"); + log(" hierarchy -check\n"); + log(" check\n"); + log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { @@ -172,15 +174,20 @@ struct SynthPass : public Pass { Pass::call(design, "opt -full"); Pass::call(design, "techmap"); Pass::call(design, "opt -fast"); + + if (!noabc) { + #ifdef YOSYS_ENABLE_ABC + Pass::call(design, "abc -fast"); + Pass::call(design, "opt -fast"); + #endif + } } - #ifdef YOSYS_ENABLE_ABC - if (check_label(active, run_from, run_to, "abc") && !noabc) + if (check_label(active, run_from, run_to, "check")) { - Pass::call(design, "abc -fast"); - Pass::call(design, "opt -fast"); + Pass::call(design, "hierarchy -check"); + Pass::call(design, "check"); } - #endif log_pop(); } |