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-rw-r--r--techlibs/common/techmap.v12
1 files changed, 12 insertions, 0 deletions
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index dc52ca5f..05074637 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -246,6 +246,18 @@ endmodule
// ALU Infrastructure
// --------------------------------------------------------
+module \$fa (A, B, C, X, Y);
+ parameter WIDTH = 1;
+
+ input [WIDTH-1:0] A, B, C;
+ output [WIDTH-1:0] X, Y;
+
+ wire [WIDTH-1:0] t1, t2, t3;
+
+ assign t1 = A ^ B, t2 = A & B, t3 = C & t1;
+ assign Y = t1 ^ C, X = t2 | t3;
+endmodule
+
module \$__alu_ripple (A, B, CI, X, Y, CO);
parameter WIDTH = 1;