summaryrefslogtreecommitdiff
path: root/techlibs/common
diff options
context:
space:
mode:
Diffstat (limited to 'techlibs/common')
-rw-r--r--techlibs/common/simlib.v45
-rw-r--r--techlibs/common/techmap.v5
2 files changed, 47 insertions, 3 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 8c0a54e4..09ffa9a6 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -467,6 +467,51 @@ endmodule
// --------------------------------------------------------
+module \$alu (A, B, CI, BI, X, Y, CO);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] X, Y;
+
+input CI, BI;
+output [Y_WIDTH-1:0] CO;
+
+wire [Y_WIDTH-1:0] AA, BB;
+
+generate
+ if (A_SIGNED && B_SIGNED) begin:BLOCK1
+ assign AA = $signed(A), BB = BI ? ~$signed(B) : $signed(B);
+ end else begin:BLOCK2
+ assign AA = $unsigned(A), BB = BI ? ~$unsigned(B) : $unsigned(B);
+ end
+endgenerate
+
+assign X = AA ^ BB;
+assign Y = AA + BB + CI;
+
+function get_carry;
+ input a, b, c;
+ get_carry = (a&b) | (a&c) | (b&c);
+endfunction
+
+genvar i;
+generate
+ assign CO[0] = get_carry(AA[0], BB[0], CI);
+ for (i = 1; i < Y_WIDTH; i = i+1) begin:BLOCK3
+ assign CO[i] = get_carry(AA[i], BB[i], CO[i-1]);
+ end
+endgenerate
+
+endmodule
+
+// --------------------------------------------------------
+
module \$lt (A, B, Y);
parameter A_SIGNED = 0;
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index 452b64b8..d6b24945 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -359,7 +359,7 @@ module \$__alu_lookahead (A, B, CI, X, Y, CO);
assign carry = {CO, CI};
endmodule
-module \$__alu (A, B, CI, BI, X, Y, CO);
+module \$alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
@@ -370,7 +370,6 @@ module \$__alu (A, B, CI, BI, X, Y, CO);
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
- // carry in, sub, carry out, carry sign
input CI, BI;
output [Y_WIDTH-1:0] CO;
@@ -410,7 +409,7 @@ endmodule
wire [WIDTH-1:0] alu_x, alu_y, alu_co;
wire [WIDTH:0] carry = {alu_co, |_sub};
- \$__alu #(
+ \$alu #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH),