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-rw-r--r--techlibs/greenpak4/Makefile.inc2
-rw-r--r--techlibs/greenpak4/cells_map.v74
-rw-r--r--techlibs/greenpak4/cells_sim.v425
-rw-r--r--techlibs/greenpak4/gp_dff.lib26
-rw-r--r--techlibs/greenpak4/greenpak4_counters.cc442
-rw-r--r--techlibs/greenpak4/greenpak4_dffinv.cc197
-rw-r--r--techlibs/greenpak4/synth_greenpak4.cc192
7 files changed, 1218 insertions, 140 deletions
diff --git a/techlibs/greenpak4/Makefile.inc b/techlibs/greenpak4/Makefile.inc
index 5808e7bd..1c9871e2 100644
--- a/techlibs/greenpak4/Makefile.inc
+++ b/techlibs/greenpak4/Makefile.inc
@@ -1,5 +1,7 @@
OBJS += techlibs/greenpak4/synth_greenpak4.o
+OBJS += techlibs/greenpak4/greenpak4_counters.o
+OBJS += techlibs/greenpak4/greenpak4_dffinv.o
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_map.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim.v))
diff --git a/techlibs/greenpak4/cells_map.v b/techlibs/greenpak4/cells_map.v
index 667d853d..111a77a1 100644
--- a/techlibs/greenpak4/cells_map.v
+++ b/techlibs/greenpak4/cells_map.v
@@ -1,20 +1,61 @@
-module \$_DFF_P_ (input D, C, output Q);
- GP_DFF _TECHMAP_REPLACE_ (
+module GP_DFFS(input D, CLK, nSET, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ GP_DFFSR #(
+ .INIT(INIT),
+ .SRMODE(1'b1),
+ ) _TECHMAP_REPLACE_ (
.D(D),
- .Q(Q),
- .CLK(C),
- .nRSTZ(1'b1),
- .nSETZ(1'b1)
+ .CLK(CLK),
+ .nSR(nSET),
+ .Q(Q)
);
endmodule
-module \$_DFFSR_PNN_ (input C, S, R, D, output Q);
- GP_DFF _TECHMAP_REPLACE_ (
+module GP_DFFR(input D, CLK, nRST, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ GP_DFFSR #(
+ .INIT(INIT),
+ .SRMODE(1'b0),
+ ) _TECHMAP_REPLACE_ (
.D(D),
- .Q(Q),
- .CLK(C),
- .nRSTZ(R),
- .nSETZ(S)
+ .CLK(CLK),
+ .nSR(nRST),
+ .Q(Q)
+ );
+endmodule
+
+module GP_DFFSI(input D, CLK, nSET, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ GP_DFFSRI #(
+ .INIT(INIT),
+ .SRMODE(1'b1),
+ ) _TECHMAP_REPLACE_ (
+ .D(D),
+ .CLK(CLK),
+ .nSR(nSET),
+ .nQ(nQ)
+ );
+endmodule
+
+module GP_DFFRI(input D, CLK, nRST, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ GP_DFFSRI #(
+ .INIT(INIT),
+ .SRMODE(1'b0),
+ ) _TECHMAP_REPLACE_ (
+ .D(D),
+ .CLK(CLK),
+ .nSR(nRST),
+ .nQ(nQ)
+ );
+endmodule
+
+module GP_OBUFT(input IN, input OE, output OUT);
+ GP_IOBUF _TECHMAP_REPLACE_ (
+ .IN(IN),
+ .OE(OE),
+ .IO(OUT),
+ .OUT()
);
endmodule
@@ -27,8 +68,13 @@ module \$lut (A, Y);
generate
if (WIDTH == 1) begin
- GP_2LUT #(.INIT({2'b00, LUT})) _TECHMAP_REPLACE_ (.OUT(Y),
- .IN0(A[0]), .IN1(1'b0));
+ if(LUT == 2'b01) begin
+ GP_INV _TECHMAP_REPLACE_ (.OUT(Y), .IN(A[0]) );
+ end
+ else begin
+ GP_2LUT #(.INIT({2'b00, LUT})) _TECHMAP_REPLACE_ (.OUT(Y),
+ .IN0(A[0]), .IN1(1'b0));
+ end
end else
if (WIDTH == 2) begin
GP_2LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index d9ddaacc..6ae9ae79 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -1,13 +1,4 @@
-module GP_DFF(input D, CLK, nRSTZ, nSETZ, output reg Q);
- always @(posedge CLK, negedge nRSTZ, negedge nSETZ) begin
- if (!nRSTZ)
- Q <= 1'b0;
- else if (!nSETZ)
- Q <= 1'b1;
- else
- Q <= D;
- end
-endmodule
+`timescale 1ns/1ps
module GP_2LUT(input IN0, IN1, output OUT);
parameter [3:0] INIT = 0;
@@ -23,3 +14,417 @@ module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
parameter [15:0] INIT = 0;
assign OUT = INIT[{IN3, IN2, IN1, IN0}];
endmodule
+
+module GP_ABUF(input wire IN, output wire OUT);
+
+ assign OUT = IN;
+
+ //cannot simulate mixed signal IP
+
+endmodule
+
+module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
+
+ parameter BANDWIDTH = "HIGH";
+ parameter VIN_ATTEN = 1;
+ parameter VIN_ISRC_EN = 0;
+ parameter HYSTERESIS = 0;
+
+ initial OUT = 0;
+
+ //cannot simulate mixed signal IP
+
+endmodule
+
+module GP_BANDGAP(output reg OK);
+ parameter AUTO_PWRDN = 1;
+ parameter CHOPPER_EN = 1;
+ parameter OUT_DELAY = 100;
+
+ //cannot simulate mixed signal IP
+
+endmodule
+
+module GP_COUNT8(input CLK, input wire RST, output reg OUT);
+
+ parameter RESET_MODE = "RISING";
+
+ parameter COUNT_TO = 8'h1;
+ parameter CLKIN_DIVIDE = 1;
+
+ //more complex hard IP blocks are not supported for simulation yet
+
+ reg[7:0] count = COUNT_TO;
+
+ //Combinatorially output whenever we wrap low
+ always @(*) begin
+ OUT <= (count == 8'h0);
+ end
+
+ //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
+ //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
+ //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
+ always @(posedge CLK) begin
+
+ count <= count - 1'd1;
+
+ if(count == 0)
+ count <= COUNT_TO;
+
+ /*
+ if((RESET_MODE == "RISING") && RST)
+ count <= 0;
+ if((RESET_MODE == "FALLING") && !RST)
+ count <= 0;
+ if((RESET_MODE == "BOTH") && RST)
+ count <= 0;
+ */
+ end
+
+endmodule
+
+module GP_COUNT14(input CLK, input wire RST, output reg OUT);
+
+ parameter RESET_MODE = "RISING";
+
+ parameter COUNT_TO = 14'h1;
+ parameter CLKIN_DIVIDE = 1;
+
+ //more complex hard IP blocks are not supported for simulation yet
+
+endmodule
+
+module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
+ input UP, input KEEP);
+
+ parameter RESET_MODE = "RISING";
+ parameter RESET_VALUE = "ZERO";
+
+ parameter COUNT_TO = 8'h1;
+ parameter CLKIN_DIVIDE = 1;
+
+ //more complex hard IP blocks are not supported for simulation yet
+
+endmodule
+
+module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
+ input UP, input KEEP);
+
+ parameter RESET_MODE = "RISING";
+ parameter RESET_VALUE = "ZERO";
+
+ parameter COUNT_TO = 14'h1;
+ parameter CLKIN_DIVIDE = 1;
+
+ //more complex hard IP blocks are not supported for simulation yet
+
+endmodule
+
+module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
+
+ initial VOUT = 0;
+
+ //analog hard IP is not supported for simulation
+
+endmodule
+
+module GP_DELAY(input IN, output reg OUT);
+
+ parameter DELAY_STEPS = 1;
+
+ //TODO: additional delay/glitch filter mode
+
+ initial OUT = 0;
+
+ generate
+
+ //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
+ //Change simulation-mode delay depending on global Vdd range (how to specify this?)
+ always @(*) begin
+ case(DELAY_STEPS)
+ 1: #166 OUT = IN;
+ 2: #318 OUT = IN;
+ 2: #471 OUT = IN;
+ 3: #622 OUT = IN;
+ default: begin
+ $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
+ $finish;
+ end
+ endcase
+ end
+
+ endgenerate
+
+endmodule
+
+module GP_DFF(input D, CLK, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ initial Q = INIT;
+ always @(posedge CLK) begin
+ Q <= D;
+ end
+endmodule
+
+module GP_DFFI(input D, CLK, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ initial nQ = INIT;
+ always @(posedge CLK) begin
+ nQ <= ~D;
+ end
+endmodule
+
+module GP_DFFR(input D, CLK, nRST, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ initial Q = INIT;
+ always @(posedge CLK, negedge nRST) begin
+ if (!nRST)
+ Q <= 1'b0;
+ else
+ Q <= D;
+ end
+endmodule
+
+module GP_DFFRI(input D, CLK, nRST, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ initial nQ = INIT;
+ always @(posedge CLK, negedge nRST) begin
+ if (!nRST)
+ nQ <= 1'b1;
+ else
+ nQ <= ~D;
+ end
+endmodule
+
+module GP_DFFS(input D, CLK, nSET, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ initial Q = INIT;
+ always @(posedge CLK, negedge nSET) begin
+ if (!nSET)
+ Q <= 1'b1;
+ else
+ Q <= D;
+ end
+endmodule
+
+module GP_DFFSI(input D, CLK, nSET, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ initial nQ = INIT;
+ always @(posedge CLK, negedge nSET) begin
+ if (!nSET)
+ nQ <= 1'b0;
+ else
+ nQ <= ~D;
+ end
+endmodule
+
+module GP_DFFSR(input D, CLK, nSR, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ parameter [0:0] SRMODE = 1'bx;
+ initial Q = INIT;
+ always @(posedge CLK, negedge nSR) begin
+ if (!nSR)
+ Q <= SRMODE;
+ else
+ Q <= D;
+ end
+endmodule
+
+module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ parameter [0:0] SRMODE = 1'bx;
+ initial nQ = INIT;
+ always @(posedge CLK, negedge nSR) begin
+ if (!nSR)
+ nQ <= ~SRMODE;
+ else
+ nQ <= ~D;
+ end
+endmodule
+
+module GP_IBUF(input IN, output OUT);
+ assign OUT = IN;
+endmodule
+
+module GP_IOBUF(input IN, input OE, output OUT, inout IO);
+ assign OUT = IO;
+ assign IO = OE ? IN : 1'bz;
+endmodule
+
+module GP_INV(input IN, output OUT);
+ assign OUT = ~IN;
+endmodule
+
+module GP_LFOSC(input PWRDN, output reg CLKOUT);
+
+ parameter PWRDN_EN = 0;
+ parameter AUTO_PWRDN = 0;
+ parameter OUT_DIV = 1;
+
+ initial CLKOUT = 0;
+
+ //auto powerdown not implemented for simulation
+ //output dividers not implemented for simulation
+
+ always begin
+ if(PWRDN)
+ CLKOUT = 0;
+ else begin
+ //half period of 1730 Hz
+ #289017;
+ CLKOUT = ~CLKOUT;
+ end
+ end
+
+endmodule
+
+module GP_OBUF(input IN, output OUT);
+ assign OUT = IN;
+endmodule
+
+module GP_OBUFT(input IN, input OE, output OUT);
+ assign OUT = OE ? IN : 1'bz;
+endmodule
+
+module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
+
+ parameter GAIN = 1;
+ parameter INPUT_MODE = "SINGLE";
+
+ initial VOUT = 0;
+
+ //cannot simulate mixed signal IP
+
+endmodule
+
+module GP_POR(output reg RST_DONE);
+ parameter POR_TIME = 500;
+
+ initial begin
+ RST_DONE = 0;
+
+ if(POR_TIME == 4)
+ #4000;
+ else if(POR_TIME == 500)
+ #500000;
+ else begin
+ $display("ERROR: bad POR_TIME for GP_POR cell");
+ $finish;
+ end
+
+ RST_DONE = 1;
+
+ end
+
+endmodule
+
+module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
+
+ parameter PWRDN_EN = 0;
+ parameter AUTO_PWRDN = 0;
+ parameter HARDIP_DIV = 1;
+ parameter FABRIC_DIV = 1;
+ parameter OSC_FREQ = "25k";
+
+ initial CLKOUT_HARDIP = 0;
+ initial CLKOUT_FABRIC = 0;
+
+ //output dividers not implemented for simulation
+ //auto powerdown not implemented for simulation
+
+ always begin
+ if(PWRDN) begin
+ CLKOUT_HARDIP = 0;
+ CLKOUT_FABRIC = 0;
+ end
+ else begin
+
+ if(OSC_FREQ == "25k") begin
+ //half period of 25 kHz
+ #20000;
+ end
+
+ else begin
+ //half period of 2 MHz
+ #250;
+ end
+
+ CLKOUT_HARDIP = ~CLKOUT_HARDIP;
+ CLKOUT_FABRIC = ~CLKOUT_FABRIC;
+ end
+ end
+
+endmodule
+
+module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
+
+ parameter PWRDN_EN = 0;
+ parameter AUTO_PWRDN = 0;
+ parameter HARDIP_DIV = 1;
+ parameter FABRIC_DIV = 1;
+
+ initial CLKOUT_HARDIP = 0;
+ initial CLKOUT_FABRIC = 0;
+
+ //output dividers not implemented for simulation
+ //auto powerdown not implemented for simulation
+
+ always begin
+ if(PWRDN) begin
+ CLKOUT_HARDIP = 0;
+ CLKOUT_FABRIC = 0;
+ end
+ else begin
+ //half period of 27 MHz
+ #18.518;
+ CLKOUT_HARDIP = ~CLKOUT_HARDIP;
+ CLKOUT_FABRIC = ~CLKOUT_FABRIC;
+ end
+ end
+
+endmodule
+
+module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
+
+ parameter OUTA_TAP = 1;
+ parameter OUTA_INVERT = 0;
+ parameter OUTB_TAP = 1;
+
+ reg[15:0] shreg = 0;
+
+ always @(posedge CLK, negedge nRST) begin
+
+ if(!nRST)
+ shreg = 0;
+
+ else
+ shreg <= {shreg[14:0], IN};
+
+ end
+
+ assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
+ assign OUTB = shreg[OUTB_TAP - 1];
+
+endmodule
+
+//keep constraint needed to prevent optimization since we have no outputs
+(* keep *)
+module GP_SYSRESET(input RST);
+ parameter RESET_MODE = "RISING";
+
+ //cannot simulate whole system reset
+
+endmodule
+
+module GP_VDD(output OUT);
+ assign OUT = 1;
+endmodule
+
+module GP_VREF(input VIN, output reg VOUT);
+ parameter VIN_DIV = 1;
+ parameter VREF = 0;
+ //cannot simulate mixed signal IP
+endmodule
+
+module GP_VSS(output OUT);
+ assign OUT = 0;
+endmodule
diff --git a/techlibs/greenpak4/gp_dff.lib b/techlibs/greenpak4/gp_dff.lib
index 9e2e46cb..b4b8c102 100644
--- a/techlibs/greenpak4/gp_dff.lib
+++ b/techlibs/greenpak4/gp_dff.lib
@@ -1,26 +1,36 @@
library(gp_dff) {
- cell(GP_DFF_NOSR) {
+ cell(GP_DFF) {
area: 1;
ff("IQ", "IQN") { clocked_on: CLK;
- next_state: D; }
+ next_state: D; }
pin(CLK) { direction: input;
- clock: true; }
+ clock: true; }
pin(D) { direction: input; }
pin(Q) { direction: output;
function: "IQ"; }
}
- cell(GP_DFF_SR) {
+ cell(GP_DFFS) {
area: 1;
ff("IQ", "IQN") { clocked_on: CLK;
next_state: D;
- preset: "nSETZ'";
- clear: "nRSTZ'"; }
+ preset: "nSET'"; }
pin(CLK) { direction: input;
clock: true; }
pin(D) { direction: input; }
pin(Q) { direction: output;
function: "IQ"; }
- pin(nRSTZ) { direction: input; }
- pin(nSETZ) { direction: input; }
+ pin(nSET) { direction: input; }
+ }
+ cell(GP_DFFR) {
+ area: 1;
+ ff("IQ", "IQN") { clocked_on: CLK;
+ next_state: D;
+ clear: "nRST'"; }
+ pin(CLK) { direction: input;
+ clock: true; }
+ pin(D) { direction: input; }
+ pin(Q) { direction: output;
+ function: "IQ"; }
+ pin(nRST) { direction: input; }
}
}
diff --git a/techlibs/greenpak4/greenpak4_counters.cc b/techlibs/greenpak4/greenpak4_counters.cc
new file mode 100644
index 00000000..998bb73b
--- /dev/null
+++ b/techlibs/greenpak4/greenpak4_counters.cc
@@ -0,0 +1,442 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2016 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+#include "kernel/modtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+//get the list of cells hooked up to at least one bit of a given net
+pool<Cell*> get_other_cells(const RTLIL::SigSpec& port, ModIndex& index, Cell* src)
+{
+ pool<Cell*> rval;
+ for(auto b : port)
+ {
+ pool<ModIndex::PortInfo> ports = index.query_ports(b);
+ for(auto x : ports)
+ {
+ if(x.cell == src)
+ continue;
+ rval.insert(x.cell);
+ }
+ }
+ return rval;
+}
+
+//return true if there is a full-width bus connection from cell a port ap to cell b port bp
+//if other_conns_allowed is false, then we require a strict point to point connection (no other links)
+bool is_full_bus(
+ const RTLIL::SigSpec& sig,
+ ModIndex& index,
+ Cell* a,
+ RTLIL::IdString ap,
+ Cell* b,
+ RTLIL::IdString bp,
+ bool other_conns_allowed = false)
+{
+ for(auto s : sig)
+ {
+ pool<ModIndex::PortInfo> ports = index.query_ports(s);
+ bool found_a = false;
+ bool found_b = false;
+ for(auto x : ports)
+ {
+ if( (x.cell == a) && (x.port == ap) )
+ found_a = true;
+ else if( (x.cell == b) && (x.port == bp) )
+ found_b = true;
+ else if(!other_conns_allowed)
+ return false;
+ }
+
+ if( (!found_a) || (!found_b) )
+ return false;
+ }
+
+ return true;
+}
+
+//return true if the signal connects to one port only (nothing on the other end)
+bool is_unconnected(const RTLIL::SigSpec& port, ModIndex& index)
+{
+ for(auto b : port)
+ {
+ pool<ModIndex::PortInfo> ports = index.query_ports(b);
+ if(ports.size() > 1)
+ return false;
+ }
+
+ return true;
+}
+
+struct CounterExtraction
+{
+ int width; //counter width
+ RTLIL::Wire* rwire; //the register output
+ bool has_reset; //true if we have a reset
+ RTLIL::SigSpec rst; //reset pin
+ int count_value; //value we count from
+ RTLIL::SigSpec clk; //clock signal
+ RTLIL::SigSpec outsig; //counter output signal
+ RTLIL::Cell* count_mux; //counter mux
+ RTLIL::Cell* count_reg; //counter register
+ RTLIL::Cell* underflow_inv; //inverter reduction for output-underflow detect
+};
+
+//attempt to extract a counter centered on the given cell
+int greenpak4_counters_tryextract(ModIndex& index, Cell *cell, CounterExtraction& extract)
+{
+ SigMap& sigmap = index.sigmap;
+
+ //GreenPak does not support counters larger than 14 bits so immediately skip anything bigger
+ int a_width = cell->getParam("\\A_WIDTH").as_int();
+ extract.width = a_width;
+ if(a_width > 14)
+ return 1;
+
+ //Second input must be a single bit
+ int b_width = cell->getParam("\\B_WIDTH").as_int();
+ if(b_width != 1)
+ return 2;
+
+ //Both inputs must be unsigned, so don't extract anything with a signed input
+ bool a_sign = cell->getParam("\\A_SIGNED").as_bool();
+ bool b_sign = cell->getParam("\\B_SIGNED").as_bool();
+ if(a_sign || b_sign)
+ return 3;
+
+ //To be a counter, one input of the ALU must be a constant 1
+ //TODO: can A or B be swapped in synthesized RTL or is B always the 1?
+ const RTLIL::SigSpec b_port = sigmap(cell->getPort("\\B"));
+ if(!b_port.is_fully_const() || (b_port.as_int() != 1) )
+ return 4;
+
+ //BI and CI must be constant 1 as well
+ const RTLIL::SigSpec bi_port = sigmap(cell->getPort("\\BI"));
+ if(!bi_port.is_fully_const() || (bi_port.as_int() != 1) )
+ return 5;
+ const RTLIL::SigSpec ci_port = sigmap(cell->getPort("\\CI"));
+ if(!ci_port.is_fully_const() || (ci_port.as_int() != 1) )
+ return 6;
+
+ //CO and X must be unconnected (exactly one connection to each port)
+ if(!is_unconnected(sigmap(cell->getPort("\\CO")), index))
+ return 7;
+ if(!is_unconnected(sigmap(cell->getPort("\\X")), index))
+ return 8;
+
+ //Y must have exactly one connection, and it has to be a $mux cell.
+ //We must have a direct bus connection from our Y to their A.
+ const RTLIL::SigSpec aluy = sigmap(cell->getPort("\\Y"));
+ pool<Cell*> y_loads = get_other_cells(aluy, index, cell);
+ if(y_loads.size() != 1)
+ return 9;
+ Cell* count_mux = *y_loads.begin();
+ extract.count_mux = count_mux;
+ if(count_mux->type != "$mux")
+ return 10;
+ if(!is_full_bus(aluy, index, cell, "\\Y", count_mux, "\\A"))
+ return 11;
+
+ //B connection of the mux is our underflow value
+ const RTLIL::SigSpec underflow = sigmap(count_mux->getPort("\\B"));
+ if(!underflow.is_fully_const())
+ return 12;
+ extract.count_value = underflow.as_int();
+
+ //S connection of the mux must come from an inverter (need not be the only load)
+ const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort("\\S"));
+ extract.outsig = muxsel;
+ pool<Cell*> muxsel_conns = get_other_cells(muxsel, index, count_mux);
+ Cell* underflow_inv = NULL;
+ for(auto c : muxsel_conns)
+ {
+ if(c->type != "$logic_not")
+ continue;
+ if(!is_full_bus(muxsel, index, c, "\\Y", count_mux, "\\S", true))
+ continue;
+
+ underflow_inv = c;
+ break;
+ }
+ if(underflow_inv == NULL)
+ return 13;
+ extract.underflow_inv = underflow_inv;
+
+ //Y connection of the mux must have exactly one load, the counter's internal register
+ const RTLIL::SigSpec muxy = sigmap(count_mux->getPort("\\Y"));
+ pool<Cell*> muxy_loads = get_other_cells(muxy, index, count_mux);
+ if(muxy_loads.size() != 1)
+ return 14;
+ Cell* count_reg = *muxy_loads.begin();
+ extract.count_reg = count_reg;
+ if(count_reg->type == "$dff")
+ extract.has_reset = false;
+ else if(count_reg->type == "$adff")
+ {
+ extract.has_reset = true;
+
+ //Verify ARST_VALUE is zero and ARST_POLARITY is 1
+ //TODO: infer an inverter to make it 1 if necessary, so we can support negative level resets?
+ if(count_reg->getParam("\\ARST_POLARITY").as_int() != 1)
+ return 22;
+ if(count_reg->getParam("\\ARST_VALUE").as_int() != 0)
+ return 23;
+
+ //Save the reset
+ extract.rst = sigmap(count_reg->getPort("\\ARST"));
+ }
+ //TODO: support synchronous reset
+ else
+ return 15;
+ if(!is_full_bus(muxy, index, count_mux, "\\Y", count_reg, "\\D"))
+ return 16;
+
+ //TODO: Verify count_reg CLK_POLARITY is 1
+
+ //Register output must have exactly two loads, the inverter and ALU
+ const RTLIL::SigSpec cnout = sigmap(count_reg->getPort("\\Q"));
+ pool<Cell*> cnout_loads = get_other_cells(cnout, index, count_reg);
+ if(cnout_loads.size() != 2)
+ return 17;
+ if(!is_full_bus(cnout, index, count_reg, "\\Q", underflow_inv, "\\A", true))
+ return 18;
+ if(!is_full_bus(cnout, index, count_reg, "\\Q", cell, "\\A", true))
+ return 19;
+
+ //Look up the clock from the register
+ extract.clk = sigmap(count_reg->getPort("\\CLK"));
+
+ //Register output net must have an INIT attribute equal to the count value
+ extract.rwire = cnout.as_wire();
+ if(extract.rwire->attributes.find("\\init") == extract.rwire->attributes.end())
+ return 20;
+ int rinit = extract.rwire->attributes["\\init"].as_int();
+ if(rinit != extract.count_value)
+ return 21;
+
+ return 0;
+}
+
+void greenpak4_counters_worker(
+ ModIndex& index,
+ Cell *cell,
+ unsigned int& total_counters,
+ pool<Cell*>& cells_to_remove)
+{
+ SigMap& sigmap = index.sigmap;
+
+ //Core of the counter must be an ALU
+ if (cell->type != "$alu")
+ return;
+
+ //A input is the count value. Check if it has COUNT_EXTRACT set.
+ //If it's not a wire, don't even try
+ auto port = sigmap(cell->getPort("\\A"));
+ if(!port.is_wire())
+ return;
+ RTLIL::Wire* a_wire = port.as_wire();
+ bool force_extract = false;
+ bool never_extract = false;
+ string count_reg_src = a_wire->attributes["\\src"].decode_string().c_str();
+ if(a_wire->attributes.find("\\COUNT_EXTRACT") != a_wire->attributes.end())
+ {
+ pool<string> sa = a_wire->get_strpool_attribute("\\COUNT_EXTRACT");
+ string extract_value;
+ if(sa.size() >= 1)
+ {
+ extract_value = *sa.begin();
+ log(" Signal %s declared at %s has COUNT_EXTRACT = %s\n",
+ log_id(a_wire),
+ count_reg_src.c_str(),
+ extract_value.c_str());
+
+ if(extract_value == "FORCE")
+ force_extract = true;
+ else if(extract_value == "NO")
+ never_extract = true;
+ else if(extract_value == "AUTO")
+ {} //default
+ else
+ log_error(" Illegal COUNT_EXTRACT value %s (must be one of FORCE, NO, AUTO)\n",
+ extract_value.c_str());
+ }
+ }
+
+ //If we're explicitly told not to extract, don't infer a counter
+ if(never_extract)
+ return;
+
+ //Attempt to extract a counter
+ CounterExtraction extract;
+ int reason = greenpak4_counters_tryextract(index, cell, extract);
+
+ //Nonzero code - we could not find a matchable counter.
+ //Do nothing, unless extraction was forced in which case give an error
+ if(reason != 0)
+ {
+ static const char* reasons[24]=
+ {
+ "no problem", //0
+ "counter is larger than 14 bits", //1
+ "counter does not count by one", //2
+ "counter uses signed math", //3
+ "counter does not count by one", //4
+ "ALU is not a subtractor", //5
+ "ALU is not a subtractor", //6
+ "ALU ports used outside counter", //7
+ "ALU ports used outside counter", //8
+ "ALU output used outside counter", //9
+ "ALU output is not a mux", //10
+ "ALU output is not full bus", //11
+ "Underflow value is not constant", //12
+ "No underflow detector found", //13
+ "Mux output is used outside counter", //14
+ "Counter reg is not DFF/ADFF", //15
+ "Counter input is not full bus", //16
+ "Count register is used outside counter", //17
+ "Register output is not full bus", //18
+ "Register output is not full bus", //19
+ "No init value found", //20
+ "Underflow value is not equal to init value", //21
+ "Reset polarity is not positive", //22
+ "Reset is not to zero" //23
+ };
+
+ if(force_extract)
+ {
+ log_error(
+ "Counter extraction is set to FORCE on register %s, but a counter could not be inferred (%s)\n",
+ log_id(a_wire),
+ reasons[reason]);
+ }
+ return;
+ }
+
+ //Figure out the final cell type based on the counter size
+ string celltype = "\\GP_COUNT8";
+ if(extract.width > 8)
+ celltype = "\\GP_COUNT14";
+
+ //Log it
+ total_counters ++;
+ string reset_type = "non-resettable";
+ if(extract.has_reset)
+ {
+ //TODO: support other kind of reset
+ reset_type = "async resettable";
+ }
+ log(" Found %d-bit %s down counter (from %d) for register %s declared at %s\n",
+ extract.width,
+ reset_type.c_str(),
+ extract.count_value,
+ log_id(extract.rwire->name),
+ count_reg_src.c_str());
+
+ //Wipe all of the old connections to the ALU
+ cell->unsetPort("\\A");
+ cell->unsetPort("\\B");
+ cell->unsetPort("\\BI");
+ cell->unsetPort("\\CI");
+ cell->unsetPort("\\CO");
+ cell->unsetPort("\\X");
+ cell->unsetPort("\\Y");
+ cell->unsetParam("\\A_SIGNED");
+ cell->unsetParam("\\A_WIDTH");
+ cell->unsetParam("\\B_SIGNED");
+ cell->unsetParam("\\B_WIDTH");
+ cell->unsetParam("\\Y_WIDTH");
+
+ //Change the cell type
+ cell->type = celltype;
+
+ //Hook up resets
+ if(extract.has_reset)
+ {
+ //TODO: support other kinds of reset
+ cell->setParam("\\RESET_MODE", RTLIL::Const("LEVEL"));
+ cell->setPort("\\RST", extract.rst);
+ }
+ else
+ {
+ cell->setParam("\\RESET_MODE", RTLIL::Const("RISING"));
+ cell->setPort("\\RST", RTLIL::SigSpec(false));
+ }
+
+ //Hook up other stuff
+ cell->setParam("\\CLKIN_DIVIDE", RTLIL::Const(1));
+ cell->setParam("\\COUNT_TO", RTLIL::Const(extract.count_value));
+
+ cell->setPort("\\CLK", extract.clk);
+ cell->setPort("\\OUT", extract.outsig);
+
+ //Delete the cells we've replaced (let opt_clean handle deleting the now-redundant wires)
+ cells_to_remove.insert(extract.count_mux);
+ cells_to_remove.insert(extract.count_reg);
+ cells_to_remove.insert(extract.underflow_inv);
+}
+
+struct Greenpak4CountersPass : public Pass {
+ Greenpak4CountersPass() : Pass("greenpak4_counters", "Extract GreenPak4 counter cells") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" greenpak4_counters [options] [selection]\n");
+ log("\n");
+ log("This pass converts non-resettable or async resettable down counters to GreenPak4\n");
+ log("counter cells (All other GreenPak4 counter modes must be instantiated manually.)\n");
+ log("\n");
+ }
+ virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ {
+ log_header(design, "Executing GREENPAK4_COUNTERS pass (mapping counters to hard IP blocks).\n");
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ // if (args[argidx] == "-v") {
+ // continue;
+ // }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ //Extract all of the counters we could find
+ unsigned int total_counters = 0;
+ for (auto module : design->selected_modules())
+ {
+ pool<Cell*> cells_to_remove;
+
+ ModIndex index(module);
+ for (auto cell : module->selected_cells())
+ greenpak4_counters_worker(index, cell, total_counters, cells_to_remove);
+
+ for(auto cell : cells_to_remove)
+ module->remove(cell);
+ }
+
+ if(total_counters)
+ log("Extracted %u counters\n", total_counters);
+ }
+} Greenpak4CountersPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/greenpak4/greenpak4_dffinv.cc b/techlibs/greenpak4/greenpak4_dffinv.cc
new file mode 100644
index 00000000..ff63958e
--- /dev/null
+++ b/techlibs/greenpak4/greenpak4_dffinv.cc
@@ -0,0 +1,197 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+void invert_gp_dff(Cell *cell, bool invert_input)
+{
+ string cell_type = cell->type.str();
+ bool cell_type_i = cell_type.find('I') != string::npos;
+ bool cell_type_r = cell_type.find('R') != string::npos;
+ bool cell_type_s = cell_type.find('S') != string::npos;
+
+ if (!invert_input)
+ {
+ Const initval = cell->getParam("\\INIT");
+ if (GetSize(initval) >= 1) {
+ if (initval.bits[0] == State::S0)
+ initval.bits[0] = State::S1;
+ else if (initval.bits[0] == State::S1)
+ initval.bits[0] = State::S0;
+ cell->setParam("\\INIT", initval);
+ }
+
+ if (cell_type_r && cell_type_s)
+ {
+ Const srmode = cell->getParam("\\SRMODE");
+ if (GetSize(srmode) >= 1) {
+ if (srmode.bits[0] == State::S0)
+ srmode.bits[0] = State::S1;
+ else if (srmode.bits[0] == State::S1)
+ srmode.bits[0] = State::S0;
+ cell->setParam("\\SRMODE", srmode);
+ }
+ }
+ else
+ {
+ if (cell_type_r) {
+ cell->setPort("\\nSET", cell->getPort("\\nRST"));
+ cell->unsetPort("\\nRST");
+ cell_type_r = false;
+ cell_type_s = true;
+ } else
+ if (cell_type_s) {
+ cell->setPort("\\nRST", cell->getPort("\\nSET"));
+ cell->unsetPort("\\nSET");
+ cell_type_r = true;
+ cell_type_s = false;
+ }
+ }
+ }
+
+ if (cell_type_i) {
+ cell->setPort("\\Q", cell->getPort("\\nQ"));
+ cell->unsetPort("\\nQ");
+ cell_type_i = false;
+ } else {
+ cell->setPort("\\nQ", cell->getPort("\\Q"));
+ cell->unsetPort("\\Q");
+ cell_type_i = true;
+ }
+
+ cell->type = stringf("\\GP_DFF%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
+
+ log("Merged %s inverter into cell %s.%s: %s -> %s\n", invert_input ? "input" : "output",
+ log_id(cell->module), log_id(cell), cell_type.c_str()+1, log_id(cell->type));
+}
+
+struct Greenpak4DffInvPass : public Pass {
+ Greenpak4DffInvPass() : Pass("greenpak4_dffinv", "merge greenpak4 inverters and DFFs") { }
+ virtual void help()
+ {
+ log("\n");
+ log(" greenpak4_dffinv [options] [selection]\n");
+ log("\n");
+ log("Merge GP_INV cells with GP_DFF* cells.\n");
+ log("\n");
+ }
+ virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ {
+ log_header(design, "Executing GREENPAK4_DFFINV pass (merge synchronous set/reset into FF cells).\n");
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ // if (args[argidx] == "-singleton") {
+ // singleton_mode = true;
+ // continue;
+ // }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ pool<IdString> gp_dff_types;
+ gp_dff_types.insert("\\GP_DFF");
+ gp_dff_types.insert("\\GP_DFFI");
+ gp_dff_types.insert("\\GP_DFFR");
+ gp_dff_types.insert("\\GP_DFFRI");
+ gp_dff_types.insert("\\GP_DFFS");
+ gp_dff_types.insert("\\GP_DFFSI");
+ gp_dff_types.insert("\\GP_DFFSR");
+ gp_dff_types.insert("\\GP_DFFSRI");
+
+ for (auto module : design->selected_modules())
+ {
+ SigMap sigmap(module);
+ dict<SigBit, int> sig_use_cnt;
+ dict<SigBit, SigBit> inv_in2out, inv_out2in;
+ dict<SigBit, Cell*> inv_in2cell;
+ pool<Cell*> dff_cells;
+
+ for (auto wire : module->wires())
+ {
+ if (!wire->port_output)
+ continue;
+
+ for (auto bit : sigmap(wire))
+ sig_use_cnt[bit]++;
+ }
+
+ for (auto cell : module->cells())
+ for (auto &conn : cell->connections())
+ if (cell->input(conn.first) || !cell->known())
+ for (auto bit : sigmap(conn.second))
+ sig_use_cnt[bit]++;
+
+ for (auto cell : module->selected_cells())
+ {
+ if (gp_dff_types.count(cell->type)) {
+ dff_cells.insert(cell);
+ continue;
+ }
+
+ if (cell->type == "\\GP_INV") {
+ SigBit in_bit = sigmap(cell->getPort("\\IN"));
+ SigBit out_bit = sigmap(cell->getPort("\\OUT"));
+ inv_in2out[in_bit] = out_bit;
+ inv_out2in[out_bit] = in_bit;
+ inv_in2cell[in_bit] = cell;
+ continue;
+ }
+ }
+
+ for (auto cell : dff_cells)
+ {
+ SigBit d_bit = sigmap(cell->getPort("\\D"));
+ SigBit q_bit = sigmap(cell->hasPort("\\Q") ? cell->getPort("\\Q") : cell->getPort("\\nQ"));
+
+ while (inv_out2in.count(d_bit))
+ {
+ sig_use_cnt[d_bit]--;
+ invert_gp_dff(cell, true);
+ d_bit = inv_out2in.at(d_bit);
+ cell->setPort("\\D", d_bit);
+ sig_use_cnt[d_bit]++;
+ }
+
+ while (inv_in2out.count(q_bit) && sig_use_cnt[q_bit] == 1)
+ {
+ SigBit new_q_bit = inv_in2out.at(q_bit);
+ module->remove(inv_in2cell.at(q_bit));
+ sig_use_cnt.erase(q_bit);
+ inv_in2out.erase(q_bit);
+ inv_out2in.erase(new_q_bit);
+ inv_in2cell.erase(q_bit);
+
+ invert_gp_dff(cell, false);
+ if (cell->hasPort("\\Q"))
+ cell->setPort("\\Q", new_q_bit);
+ else
+ cell->setPort("\\nQ", new_q_bit);
+ }
+ }
+ }
+ }
+} Greenpak4DffInvPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc
index 15b53d62..10e2a149 100644
--- a/techlibs/greenpak4/synth_greenpak4.cc
+++ b/techlibs/greenpak4/synth_greenpak4.cc
@@ -25,18 +25,11 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
-bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
+struct SynthGreenPAK4Pass : public ScriptPass
{
- if (label == run_from)
- active = true;
- if (label == run_to)
- active = false;
- return active;
-}
-
-struct SynthGreenPAK4Pass : public Pass {
- SynthGreenPAK4Pass() : Pass("synth_greenpak4", "synthesis for GreenPAK4 FPGAs") { }
- virtual void help()
+ SynthGreenPAK4Pass() : ScriptPass("synth_greenpak4", "synthesis for GreenPAK4 FPGAs") { }
+
+ virtual void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -47,12 +40,12 @@ struct SynthGreenPAK4Pass : public Pass {
log(" -top <module>\n");
log(" use the specified module as top module (default='top')\n");
log("\n");
- log(" -blif <file>\n");
- log(" write the design to the specified BLIF file. writing of an output file\n");
- log(" is omitted if this parameter is not specified.\n");
+ log(" -part <part>\n");
+ log(" synthesize for the specified part. Valid values are SLG46140V,\n");
+ log(" SLG46620V, and SLG46621V (default).\n");
log("\n");
- log(" -edif <file>\n");
- log(" write the design to the specified edif file. writing of an output file\n");
+ log(" -json <file>\n");
+ log(" write the design to the specified JSON file. writing of an output file\n");
log(" is omitted if this parameter is not specified.\n");
log("\n");
log(" -run <from_label>:<to_label>\n");
@@ -68,55 +61,26 @@ struct SynthGreenPAK4Pass : public Pass {
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
+ help_script();
log("\n");
- log(" begin:\n");
- log(" read_verilog -lib +/greenpak4/cells_sim.v\n");
- log(" hierarchy -check -top <top>\n");
- log("\n");
- log(" flatten: (unless -noflatten)\n");
- log(" proc\n");
- log(" flatten\n");
- log(" tribuf -logic\n");
- log("\n");
- log(" coarse:\n");
- log(" synth -run coarse\n");
- log("\n");
- log(" fine:\n");
- log(" opt -fast -mux_undef -undriven -fine\n");
- log(" memory_map\n");
- log(" opt -undriven -fine\n");
- log(" techmap\n");
- log(" dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib\n");
- log(" opt -fast\n");
- log(" abc -dff (only if -retime)\n");
- log("\n");
- log(" map_luts:\n");
- log(" nlutmap -luts 0,8,16,2\n");
- log(" clean\n");
- log("\n");
- log(" map_cells:\n");
- log(" techmap -map +/greenpak4/cells_map.v\n");
- log(" clean\n");
- log("\n");
- log(" check:\n");
- log(" hierarchy -check\n");
- log(" stat\n");
- log(" check -noinit\n");
- log("\n");
- log(" blif:\n");
- log(" write_blif -gates -attr -param <file-name>\n");
- log("\n");
- log(" edif:\n");
- log(" write_edif <file-name>\n");
- log("\n");
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+
+ string top_opt, part, json_file;
+ bool flatten, retime;
+
+ virtual void clear_flags() YS_OVERRIDE
+ {
+ top_opt = "-auto-top";
+ part = "SLG46621V";
+ json_file = "";
+ flatten = true;
+ retime = false;
+ }
+
+ virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
- std::string top_opt = "-auto-top";
- std::string run_from, run_to;
- std::string blif_file, edif_file;
- bool flatten = true;
- bool retime = false;
+ string run_from, run_to;
+ clear_flags();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@@ -125,12 +89,12 @@ struct SynthGreenPAK4Pass : public Pass {
top_opt = "-top " + args[++argidx];
continue;
}
- if (args[argidx] == "-blif" && argidx+1 < args.size()) {
- blif_file = args[++argidx];
+ if (args[argidx] == "-json" && argidx+1 < args.size()) {
+ json_file = args[++argidx];
continue;
}
- if (args[argidx] == "-edif" && argidx+1 < args.size()) {
- edif_file = args[++argidx];
+ if (args[argidx] == "-part" && argidx+1 < args.size()) {
+ part = args[++argidx];
continue;
}
if (args[argidx] == "-run" && argidx+1 < args.size()) {
@@ -141,10 +105,6 @@ struct SynthGreenPAK4Pass : public Pass {
run_to = args[argidx].substr(pos+1);
continue;
}
- if (args[argidx] == "-flatten") {
- flatten = true;
- continue;
- }
if (args[argidx] == "-noflatten") {
flatten = false;
continue;
@@ -160,70 +120,86 @@ struct SynthGreenPAK4Pass : public Pass {
if (!design->full_selection())
log_cmd_error("This comannd only operates on fully selected designs!\n");
- bool active = run_from.empty();
+ if (part != "SLG46140V" && part != "SLG46620V" && part != "SLG46621V")
+ log_cmd_error("Invalid part name: '%s'\n", part.c_str());
- log_header("Executing SYNTH_GREENPAK4 pass.\n");
+ log_header(design, "Executing SYNTH_GREENPAK4 pass.\n");
log_push();
- if (check_label(active, run_from, run_to, "begin"))
- {
- Pass::call(design, "read_verilog -lib +/greenpak4/cells_sim.v");
- Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str()));
- }
+ run_script(design, run_from, run_to);
+
+ log_pop();
+ }
- if (flatten && check_label(active, run_from, run_to, "flatten"))
+ virtual void script() YS_OVERRIDE
+ {
+ if (check_label("begin"))
{
- Pass::call(design, "proc");
- Pass::call(design, "flatten");
- Pass::call(design, "tribuf -logic");
+ run("read_verilog -lib +/greenpak4/cells_sim.v");
+ run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
}
- if (check_label(active, run_from, run_to, "coarse"))
+ if (flatten && check_label("flatten", "(unless -noflatten)"))
{
- Pass::call(design, "synth -run coarse");
+ run("proc");
+ run("flatten");
+ run("tribuf -logic");
}
- if (check_label(active, run_from, run_to, "fine"))
+ if (check_label("coarse"))
{
- Pass::call(design, "opt -fast -mux_undef -undriven -fine");
- Pass::call(design, "memory_map");
- Pass::call(design, "opt -undriven -fine");
- Pass::call(design, "techmap");
- Pass::call(design, "dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib");
- Pass::call(design, "opt -fast");
- if (retime)
- Pass::call(design, "abc -dff");
+ run("synth -run coarse");
}
- if (check_label(active, run_from, run_to, "map_luts"))
+ if (check_label("fine"))
{
- Pass::call(design, "nlutmap -luts 0,8,16,2");
- Pass::call(design, "clean");
+ run("greenpak4_counters");
+ run("clean");
+ run("opt -fast -mux_undef -undriven -fine");
+ run("memory_map");
+ run("opt -undriven -fine");
+ run("techmap");
+ run("dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib");
+ run("opt -fast");
+ if (retime || help_mode)
+ run("abc -dff", "(only if -retime)");
}
- if (check_label(active, run_from, run_to, "map_cells"))
+ if (check_label("map_luts"))
{
- Pass::call(design, "techmap -map +/greenpak4/cells_map.v");
- Pass::call(design, "clean");
+ if (help_mode || part == "SLG46140V") run("nlutmap -assert -luts 0,6,8,2", " (for -part SLG46140V)");
+ if (help_mode || part == "SLG46620V") run("nlutmap -assert -luts 2,8,16,2", "(for -part SLG46620V)");
+ if (help_mode || part == "SLG46621V") run("nlutmap -assert -luts 2,8,16,2", "(for -part SLG46621V)");
+ run("clean");
}
- if (check_label(active, run_from, run_to, "check"))
+ if (check_label("map_cells"))
{
- Pass::call(design, "hierarchy -check");
- Pass::call(design, "stat");
- Pass::call(design, "check -noinit");
+ run("shregmap -tech greenpak4");
+ run("dfflibmap -liberty +/greenpak4/gp_dff.lib");
+ run("dffinit -ff GP_DFF Q INIT");
+ run("dffinit -ff GP_DFFR Q INIT");
+ run("dffinit -ff GP_DFFS Q INIT");
+ run("dffinit -ff GP_DFFSR Q INIT");
+ run("iopadmap -bits -inpad GP_IBUF OUT:IN -outpad GP_OBUF IN:OUT -inoutpad GP_OBUF OUT:IN -toutpad GP_OBUFT OE:IN:OUT -tinoutpad GP_IOBUF OE:OUT:IN:IO");
+ run("attrmvcp -attr src -attr LOC t:GP_OBUF t:GP_OBUFT t:GP_IOBUF n:*");
+ run("attrmvcp -attr src -attr LOC -driven t:GP_IBUF n:*");
+ run("techmap -map +/greenpak4/cells_map.v");
+ run("greenpak4_dffinv");
+ run("clean");
}
- if (check_label(active, run_from, run_to, "blif"))
+ if (check_label("check"))
{
- if (!blif_file.empty())
- Pass::call(design, stringf("write_blif -gates -attr -param %s", blif_file.c_str()));
+ run("hierarchy -check");
+ run("stat");
+ run("check -noinit");
}
- if (check_label(active, run_from, run_to, "edif"))
+ if (check_label("json"))
{
- if (!edif_file.empty())
- Pass::call(design, stringf("write_edif %s", edif_file.c_str()));
+ if (!json_file.empty() || help_mode)
+ run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
}
log_pop();
generated by cgit v1.2.3 (git 2.25.1) at 2023-03-21 05:37:00 +0000