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-rw-r--r--techlibs/greenpak4/Makefile.inc6
-rw-r--r--techlibs/greenpak4/cells_blackbox.v18
-rw-r--r--techlibs/greenpak4/cells_latch.v15
-rw-r--r--techlibs/greenpak4/cells_map.v165
-rw-r--r--techlibs/greenpak4/cells_sim.v462
-rw-r--r--techlibs/greenpak4/cells_sim_ams.v110
-rw-r--r--techlibs/greenpak4/cells_sim_digital.v794
-rw-r--r--techlibs/greenpak4/cells_sim_wip.v136
-rw-r--r--techlibs/greenpak4/greenpak4_counters.cc442
-rw-r--r--techlibs/greenpak4/greenpak4_dffinv.cc25
-rw-r--r--techlibs/greenpak4/synth_greenpak4.cc15
11 files changed, 1273 insertions, 915 deletions
diff --git a/techlibs/greenpak4/Makefile.inc b/techlibs/greenpak4/Makefile.inc
index 1c9871e2..b43fb751 100644
--- a/techlibs/greenpak4/Makefile.inc
+++ b/techlibs/greenpak4/Makefile.inc
@@ -1,8 +1,12 @@
OBJS += techlibs/greenpak4/synth_greenpak4.o
-OBJS += techlibs/greenpak4/greenpak4_counters.o
OBJS += techlibs/greenpak4/greenpak4_dffinv.o
+$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_blackbox.v))
+$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_latch.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_map.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim.v))
+$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim_ams.v))
+$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim_digital.v))
+$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim_wip.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/gp_dff.lib))
diff --git a/techlibs/greenpak4/cells_blackbox.v b/techlibs/greenpak4/cells_blackbox.v
new file mode 100644
index 00000000..1895b90d
--- /dev/null
+++ b/techlibs/greenpak4/cells_blackbox.v
@@ -0,0 +1,18 @@
+module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
+
+ input wire CE;
+ input wire CLK;
+ output reg OUT;
+ output reg[WIDTH-1:0] POUT;
+ input wire RST;
+ input wire UP;
+
+ parameter COUNT_TO = 1;
+ parameter RESET_MODE = "RISING";
+ parameter RESET_TO_MAX = "1";
+ parameter HAS_POUT = 0;
+ parameter HAS_CE = 0;
+ parameter WIDTH = 8;
+ parameter DIRECTION = "DOWN";
+
+endmodule
diff --git a/techlibs/greenpak4/cells_latch.v b/techlibs/greenpak4/cells_latch.v
new file mode 100644
index 00000000..2ccdd203
--- /dev/null
+++ b/techlibs/greenpak4/cells_latch.v
@@ -0,0 +1,15 @@
+module $_DLATCH_P_(input E, input D, output Q);
+ GP_DLATCH _TECHMAP_REPLACE_ (
+ .D(D),
+ .nCLK(!E),
+ .Q(Q)
+ );
+endmodule
+
+module $_DLATCH_N_(input E, input D, output Q);
+ GP_DLATCH _TECHMAP_REPLACE_ (
+ .D(D),
+ .nCLK(E),
+ .Q(Q)
+ );
+endmodule
diff --git a/techlibs/greenpak4/cells_map.v b/techlibs/greenpak4/cells_map.v
index 111a77a1..b971a51f 100644
--- a/techlibs/greenpak4/cells_map.v
+++ b/techlibs/greenpak4/cells_map.v
@@ -50,6 +50,58 @@ module GP_DFFRI(input D, CLK, nRST, output reg nQ);
);
endmodule
+module GP_DLATCHS(input D, nCLK, nSET, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ GP_DLATCHSR #(
+ .INIT(INIT),
+ .SRMODE(1'b1),
+ ) _TECHMAP_REPLACE_ (
+ .D(D),
+ .nCLK(nCLK),
+ .nSR(nSET),
+ .Q(Q)
+ );
+endmodule
+
+module GP_DLATCHR(input D, nCLK, nRST, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ GP_DLATCHSR #(
+ .INIT(INIT),
+ .SRMODE(1'b0),
+ ) _TECHMAP_REPLACE_ (
+ .D(D),
+ .nCLK(nCLK),
+ .nSR(nRST),
+ .Q(Q)
+ );
+endmodule
+
+module GP_DLATCHSI(input D, nCLK, nSET, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ GP_DLATCHSRI #(
+ .INIT(INIT),
+ .SRMODE(1'b1),
+ ) _TECHMAP_REPLACE_ (
+ .D(D),
+ .nCLK(nCLK),
+ .nSR(nSET),
+ .nQ(nQ)
+ );
+endmodule
+
+module GP_DLATCHRI(input D, nCLK, nRST, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ GP_DLATCHSRI #(
+ .INIT(INIT),
+ .SRMODE(1'b0),
+ ) _TECHMAP_REPLACE_ (
+ .D(D),
+ .nCLK(nCLK),
+ .nSR(nRST),
+ .nQ(nQ)
+ );
+endmodule
+
module GP_OBUFT(input IN, input OE, output OUT);
GP_IOBUF _TECHMAP_REPLACE_ (
.IN(IN),
@@ -92,3 +144,116 @@ module \$lut (A, Y);
end
endgenerate
endmodule
+
+module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
+
+ input wire CE;
+ input wire CLK;
+ output reg OUT;
+ output reg[WIDTH-1:0] POUT;
+ input wire RST;
+ input wire UP;
+
+ parameter COUNT_TO = 1;
+ parameter RESET_MODE = "RISING";
+ parameter RESET_TO_MAX = 0;
+ parameter HAS_POUT = 0;
+ parameter HAS_CE = 0;
+ parameter WIDTH = 8;
+ parameter DIRECTION = "DOWN";
+
+ //If we have a DIRECTION other than DOWN fail... GP_COUNTx_ADV is not supported yet
+ if(DIRECTION != "DOWN") begin
+ initial begin
+ $display("ERROR: \$__COUNT_ support for GP_COUNTx_ADV is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?).");
+ $finish;
+ end
+ end
+
+ //If counter is more than 14 bits wide, complain (also shouldn't happen)
+ else if(WIDTH > 14) begin
+ initial begin
+ $display("ERROR: \$__COUNT_ support for cascaded counters is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?).");
+ $finish;
+ end
+ end
+
+ //If counter is more than 8 bits wide and has parallel output, we have a problem
+ else if(WIDTH > 8 && HAS_POUT) begin
+ initial begin
+ $display("ERROR: \$__COUNT_ support for 9-14 bit counters with parallel output is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?).");
+ $finish;
+ end
+ end
+
+ //Looks like a legal counter! Do something with it
+ else if(WIDTH <= 8) begin
+ if(HAS_CE) begin
+ wire ce_not;
+ GP_INV ceinv(
+ .IN(CE),
+ .OUT(ce_not)
+ );
+ GP_COUNT8_ADV #(
+ .COUNT_TO(COUNT_TO),
+ .RESET_MODE(RESET_MODE),
+ .RESET_VALUE(RESET_TO_MAX ? "COUNT_TO" : "ZERO"),
+ .CLKIN_DIVIDE(1)
+ ) _TECHMAP_REPLACE_ (
+ .CLK(CLK),
+ .RST(RST),
+ .OUT(OUT),
+ .UP(1'b0), //always count down for now
+ .KEEP(ce_not),
+ .POUT(POUT)
+ );
+ end
+ else begin
+ GP_COUNT8 #(
+ .COUNT_TO(COUNT_TO),
+ .RESET_MODE(RESET_MODE),
+ .CLKIN_DIVIDE(1)
+ ) _TECHMAP_REPLACE_ (
+ .CLK(CLK),
+ .RST(RST),
+ .OUT(OUT),
+ .POUT(POUT)
+ );
+ end
+ end
+
+ else begin
+ if(HAS_CE) begin
+ wire ce_not;
+ GP_INV ceinv(
+ .IN(CE),
+ .OUT(ce_not)
+ );
+ GP_COUNT14_ADV #(
+ .COUNT_TO(COUNT_TO),
+ .RESET_MODE(RESET_TO_MAX ? "COUNT_TO" : "ZERO"),
+ .RESET_VALUE("COUNT_TO"),
+ .CLKIN_DIVIDE(1)
+ ) _TECHMAP_REPLACE_ (
+ .CLK(CLK),
+ .RST(RST),
+ .OUT(OUT),
+ .UP(1'b0), //always count down for now
+ .KEEP(ce_not),
+ .POUT(POUT)
+ );
+ end
+ else begin
+ GP_COUNT14 #(
+ .COUNT_TO(COUNT_TO),
+ .RESET_MODE(RESET_MODE),
+ .CLKIN_DIVIDE(1)
+ ) _TECHMAP_REPLACE_ (
+ .CLK(CLK),
+ .RST(RST),
+ .OUT(OUT)
+ );
+ end
+ end
+
+endmodule
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 80746be0..221bee69 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -1,461 +1,5 @@
`timescale 1ns/1ps
-module GP_2LUT(input IN0, IN1, output OUT);
- parameter [3:0] INIT = 0;
- assign OUT = INIT[{IN1, IN0}];
-endmodule
-
-module GP_3LUT(input IN0, IN1, IN2, output OUT);
- parameter [7:0] INIT = 0;
- assign OUT = INIT[{IN2, IN1, IN0}];
-endmodule
-
-module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
- parameter [15:0] INIT = 0;
- assign OUT = INIT[{IN3, IN2, IN1, IN0}];
-endmodule
-
-module GP_ABUF(input wire IN, output wire OUT);
-
- assign OUT = IN;
-
- //cannot simulate mixed signal IP
-
-endmodule
-
-module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
-
- parameter BANDWIDTH = "HIGH";
- parameter VIN_ATTEN = 1;
- parameter VIN_ISRC_EN = 0;
- parameter HYSTERESIS = 0;
-
- initial OUT = 0;
-
- //cannot simulate mixed signal IP
-
-endmodule
-
-module GP_BANDGAP(output reg OK);
- parameter AUTO_PWRDN = 1;
- parameter CHOPPER_EN = 1;
- parameter OUT_DELAY = 100;
-
- //cannot simulate mixed signal IP
-
-endmodule
-
-module GP_COUNT8(input CLK, input wire RST, output reg OUT);
-
- parameter RESET_MODE = "RISING";
-
- parameter COUNT_TO = 8'h1;
- parameter CLKIN_DIVIDE = 1;
-
- //more complex hard IP blocks are not supported for simulation yet
-
- reg[7:0] count = COUNT_TO;
-
- //Combinatorially output whenever we wrap low
- always @(*) begin
- OUT <= (count == 8'h0);
- end
-
- //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
- //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
- //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
- always @(posedge CLK) begin
-
- count <= count - 1'd1;
-
- if(count == 0)
- count <= COUNT_TO;
-
- /*
- if((RESET_MODE == "RISING") && RST)
- count <= 0;
- if((RESET_MODE == "FALLING") && !RST)
- count <= 0;
- if((RESET_MODE == "BOTH") && RST)
- count <= 0;
- */
- end
-
-endmodule
-
-module GP_COUNT14(input CLK, input wire RST, output reg OUT);
-
- parameter RESET_MODE = "RISING";
-
- parameter COUNT_TO = 14'h1;
- parameter CLKIN_DIVIDE = 1;
-
- //more complex hard IP blocks are not supported for simulation yet
-
-endmodule
-
-module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
- input UP, input KEEP);
-
- parameter RESET_MODE = "RISING";
- parameter RESET_VALUE = "ZERO";
-
- parameter COUNT_TO = 8'h1;
- parameter CLKIN_DIVIDE = 1;
-
- //more complex hard IP blocks are not supported for simulation yet
-
-endmodule
-
-module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
- input UP, input KEEP);
-
- parameter RESET_MODE = "RISING";
- parameter RESET_VALUE = "ZERO";
-
- parameter COUNT_TO = 14'h1;
- parameter CLKIN_DIVIDE = 1;
-
- //more complex hard IP blocks are not supported for simulation yet
-
-endmodule
-
-module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
-
- initial VOUT = 0;
-
- //analog hard IP is not supported for simulation
-
-endmodule
-
-module GP_DELAY(input IN, output reg OUT);
-
- parameter DELAY_STEPS = 1;
- parameter GLITCH_FILTER = 0;
-
- initial OUT = 0;
-
- generate
-
- //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
- //Change simulation-mode delay depending on global Vdd range (how to specify this?)
- always @(*) begin
- case(DELAY_STEPS)
- 1: #166 OUT = IN;
- 2: #318 OUT = IN;
- 2: #471 OUT = IN;
- 3: #622 OUT = IN;
- default: begin
- $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
- $finish;
- end
- endcase
- end
-
- endgenerate
-
-endmodule
-
-module GP_DFF(input D, CLK, output reg Q);
- parameter [0:0] INIT = 1'bx;
- initial Q = INIT;
- always @(posedge CLK) begin
- Q <= D;
- end
-endmodule
-
-module GP_DFFI(input D, CLK, output reg nQ);
- parameter [0:0] INIT = 1'bx;
- initial nQ = INIT;
- always @(posedge CLK) begin
- nQ <= ~D;
- end
-endmodule
-
-module GP_DFFR(input D, CLK, nRST, output reg Q);
- parameter [0:0] INIT = 1'bx;
- initial Q = INIT;
- always @(posedge CLK, negedge nRST) begin
- if (!nRST)
- Q <= 1'b0;
- else
- Q <= D;
- end
-endmodule
-
-module GP_DFFRI(input D, CLK, nRST, output reg nQ);
- parameter [0:0] INIT = 1'bx;
- initial nQ = INIT;
- always @(posedge CLK, negedge nRST) begin
- if (!nRST)
- nQ <= 1'b1;
- else
- nQ <= ~D;
- end
-endmodule
-
-module GP_DFFS(input D, CLK, nSET, output reg Q);
- parameter [0:0] INIT = 1'bx;
- initial Q = INIT;
- always @(posedge CLK, negedge nSET) begin
- if (!nSET)
- Q <= 1'b1;
- else
- Q <= D;
- end
-endmodule
-
-module GP_DFFSI(input D, CLK, nSET, output reg nQ);
- parameter [0:0] INIT = 1'bx;
- initial nQ = INIT;
- always @(posedge CLK, negedge nSET) begin
- if (!nSET)
- nQ <= 1'b0;
- else
- nQ <= ~D;
- end
-endmodule
-
-module GP_DFFSR(input D, CLK, nSR, output reg Q);
- parameter [0:0] INIT = 1'bx;
- parameter [0:0] SRMODE = 1'bx;
- initial Q = INIT;
- always @(posedge CLK, negedge nSR) begin
- if (!nSR)
- Q <= SRMODE;
- else
- Q <= D;
- end
-endmodule
-
-module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
- parameter [0:0] INIT = 1'bx;
- parameter [0:0] SRMODE = 1'bx;
- initial nQ = INIT;
- always @(posedge CLK, negedge nSR) begin
- if (!nSR)
- nQ <= ~SRMODE;
- else
- nQ <= ~D;
- end
-endmodule
-
-module GP_EDGEDET(input IN, output reg OUT);
-
- parameter EDGE_DIRECTION = "RISING";
- parameter DELAY_STEPS = 1;
- parameter GLITCH_FILTER = 0;
-
- //not implemented for simulation
-
-endmodule
-
-module GP_IBUF(input IN, output OUT);
- assign OUT = IN;
-endmodule
-
-module GP_IOBUF(input IN, input OE, output OUT, inout IO);
- assign OUT = IO;
- assign IO = OE ? IN : 1'bz;
-endmodule
-
-module GP_INV(input IN, output OUT);
- assign OUT = ~IN;
-endmodule
-
-module GP_LFOSC(input PWRDN, output reg CLKOUT);
-
- parameter PWRDN_EN = 0;
- parameter AUTO_PWRDN = 0;
- parameter OUT_DIV = 1;
-
- initial CLKOUT = 0;
-
- //auto powerdown not implemented for simulation
- //output dividers not implemented for simulation
-
- always begin
- if(PWRDN)
- CLKOUT = 0;
- else begin
- //half period of 1730 Hz
- #289017;
- CLKOUT = ~CLKOUT;
- end
- end
-
-endmodule
-
-module GP_OBUF(input IN, output OUT);
- assign OUT = IN;
-endmodule
-
-module GP_OBUFT(input IN, input OE, output OUT);
- assign OUT = OE ? IN : 1'bz;
-endmodule
-
-module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
-
- parameter GAIN = 1;
- parameter INPUT_MODE = "SINGLE";
-
- initial VOUT = 0;
-
- //cannot simulate mixed signal IP
-
-endmodule
-
-module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
- initial OUT = 0;
- parameter PATTERN_DATA = 16'h0;
- parameter PATTERN_LEN = 5'd16;
-
- reg[3:0] count = 0;
- always @(posedge CLK) begin
- if(!nRST)
- OUT <= PATTERN_DATA[0];
-
- else begin
- count <= count + 1;
- OUT <= PATTERN_DATA[count];
-
- if( (count + 1) == PATTERN_LEN)
- count <= 0;
- end
- end
-
-endmodule
-
-module GP_POR(output reg RST_DONE);
- parameter POR_TIME = 500;
-
- initial begin
- RST_DONE = 0;
-
- if(POR_TIME == 4)
- #4000;
- else if(POR_TIME == 500)
- #500000;
- else begin
- $display("ERROR: bad POR_TIME for GP_POR cell");
- $finish;
- end
-
- RST_DONE = 1;
-
- end
-
-endmodule
-
-module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
-
- parameter PWRDN_EN = 0;
- parameter AUTO_PWRDN = 0;
- parameter HARDIP_DIV = 1;
- parameter FABRIC_DIV = 1;
- parameter OSC_FREQ = "25k";
-
- initial CLKOUT_HARDIP = 0;
- initial CLKOUT_FABRIC = 0;
-
- //output dividers not implemented for simulation
- //auto powerdown not implemented for simulation
-
- always begin
- if(PWRDN) begin
- CLKOUT_HARDIP = 0;
- CLKOUT_FABRIC = 0;
- end
- else begin
-
- if(OSC_FREQ == "25k") begin
- //half period of 25 kHz
- #20000;
- end
-
- else begin
- //half period of 2 MHz
- #250;
- end
-
- CLKOUT_HARDIP = ~CLKOUT_HARDIP;
- CLKOUT_FABRIC = ~CLKOUT_FABRIC;
- end
- end
-
-endmodule
-
-module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
-
- parameter PWRDN_EN = 0;
- parameter AUTO_PWRDN = 0;
- parameter HARDIP_DIV = 1;
- parameter FABRIC_DIV = 1;
-
- initial CLKOUT_HARDIP = 0;
- initial CLKOUT_FABRIC = 0;
-
- //output dividers not implemented for simulation
- //auto powerdown not implemented for simulation
-
- always begin
- if(PWRDN) begin
- CLKOUT_HARDIP = 0;
- CLKOUT_FABRIC = 0;
- end
- else begin
- //half period of 27 MHz
- #18.518;
- CLKOUT_HARDIP = ~CLKOUT_HARDIP;
- CLKOUT_FABRIC = ~CLKOUT_FABRIC;
- end
- end
-
-endmodule
-
-module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
-
- parameter OUTA_TAP = 1;
- parameter OUTA_INVERT = 0;
- parameter OUTB_TAP = 1;
-
- reg[15:0] shreg = 0;
-
- always @(posedge CLK, negedge nRST) begin
-
- if(!nRST)
- shreg = 0;
-
- else
- shreg <= {shreg[14:0], IN};
-
- end
-
- assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
- assign OUTB = shreg[OUTB_TAP - 1];
-
-endmodule
-
-//keep constraint needed to prevent optimization since we have no outputs
-(* keep *)
-module GP_SYSRESET(input RST);
- parameter RESET_MODE = "EDGE";
- parameter EDGE_SPEED = 4;
-
- //cannot simulate whole system reset
-
-endmodule
-
-module GP_VDD(output OUT);
- assign OUT = 1;
-endmodule
-
-module GP_VREF(input VIN, output reg VOUT);
- parameter VIN_DIV = 1;
- parameter VREF = 0;
- //cannot simulate mixed signal IP
-endmodule
-
-module GP_VSS(output OUT);
- assign OUT = 0;
-endmodule
+`include "cells_sim_ams.v"
+`include "cells_sim_digital.v"
+`include "cells_sim_wip.v"
diff --git a/techlibs/greenpak4/cells_sim_ams.v b/techlibs/greenpak4/cells_sim_ams.v
new file mode 100644
index 00000000..7f8b3de3
--- /dev/null
+++ b/techlibs/greenpak4/cells_sim_ams.v
@@ -0,0 +1,110 @@
+`timescale 1ns/1ps
+
+/*
+ This file contains analog / mixed signal cells, or other things that are not possible to fully model
+ in behavioral Verilog.
+
+ It also contains some stuff like oscillators that use non-synthesizeable constructs such as delays.
+ TODO: do we want a third file for those cells?
+ */
+
+module GP_ABUF(input wire IN, output wire OUT);
+
+ assign OUT = IN;
+
+ //must be 1, 5, 20, 50
+ //values >1 only available with Vdd > 2.7V
+ parameter BANDWIDTH_KHZ = 1;
+
+endmodule
+
+module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
+
+ parameter BANDWIDTH = "HIGH";
+ parameter VIN_ATTEN = 1;
+ parameter VIN_ISRC_EN = 0;
+ parameter HYSTERESIS = 0;
+
+ initial OUT = 0;
+
+endmodule
+
+module GP_BANDGAP(output reg OK);
+ parameter AUTO_PWRDN = 1;
+ parameter CHOPPER_EN = 1;
+ parameter OUT_DELAY = 100;
+
+endmodule
+
+module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
+
+ initial VOUT = 0;
+
+ //analog hard IP is not supported for simulation
+
+endmodule
+
+module GP_LFOSC(input PWRDN, output reg CLKOUT);
+
+ parameter PWRDN_EN = 0;
+ parameter AUTO_PWRDN = 0;
+ parameter OUT_DIV = 1;
+
+ initial CLKOUT = 0;
+
+ //auto powerdown not implemented for simulation
+ //output dividers not implemented for simulation
+
+ always begin
+ if(PWRDN)
+ CLKOUT = 0;
+ else begin
+ //half period of 1730 Hz
+ #289017;
+ CLKOUT = ~CLKOUT;
+ end
+ end
+
+endmodule
+
+module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
+
+ parameter GAIN = 1;
+ parameter INPUT_MODE = "SINGLE";
+
+ initial VOUT = 0;
+
+ //cannot simulate mixed signal IP
+
+endmodule
+
+module GP_PWRDET(output reg VDD_LOW);
+ initial VDD_LOW = 0;
+endmodule
+
+module GP_VREF(input VIN, output reg VOUT);
+ parameter VIN_DIV = 1;
+ parameter VREF = 0;
+ //cannot simulate mixed signal IP
+endmodule
+
+module GP_POR(output reg RST_DONE);
+ parameter POR_TIME = 500;
+
+ initial begin
+ RST_DONE = 0;
+
+ if(POR_TIME == 4)
+ #4000;
+ else if(POR_TIME == 500)
+ #500000;
+ else begin
+ $display("ERROR: bad POR_TIME for GP_POR cell");
+ $finish;
+ end
+
+ RST_DONE = 1;
+
+ end
+
+endmodule
diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v
new file mode 100644
index 00000000..43d35d08
--- /dev/null
+++ b/techlibs/greenpak4/cells_sim_digital.v
@@ -0,0 +1,794 @@
+`timescale 1ns/1ps
+
+/*
+ This file contains simulation models for GreenPAK cells which are possible to fully model using synthesizeable
+ behavioral Verilog constructs only.
+ */
+
+module GP_2LUT(input IN0, IN1, output OUT);
+ parameter [3:0] INIT = 0;
+ assign OUT = INIT[{IN1, IN0}];
+endmodule
+
+module GP_3LUT(input IN0, IN1, IN2, output OUT);
+ parameter [7:0] INIT = 0;
+ assign OUT = INIT[{IN2, IN1, IN0}];
+endmodule
+
+module GP_4LUT(
+ input wire IN0,
+ input wire IN1,
+ input wire IN2,
+ input wire IN3,
+ output wire OUT);
+
+ parameter [15:0] INIT = 0;
+ assign OUT = INIT[{IN3, IN2, IN1, IN0}];
+endmodule
+
+module GP_CLKBUF(input wire IN, output wire OUT);
+ assign OUT = IN;
+endmodule
+
+module GP_COUNT14(input CLK, input wire RST, output reg OUT);
+
+ parameter RESET_MODE = "RISING";
+
+ parameter COUNT_TO = 14'h1;
+ parameter CLKIN_DIVIDE = 1;
+
+ reg[13:0] count = COUNT_TO;
+
+ initial begin
+ if(CLKIN_DIVIDE != 1) begin
+ $display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
+ $finish;
+ end
+ end
+
+ //Combinatorially output underflow flag whenever we wrap low
+ always @(*) begin
+ OUT <= (count == 14'h0);
+ end
+
+ //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
+ //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
+ generate
+ case(RESET_MODE)
+
+ "RISING": begin
+ always @(posedge CLK, posedge RST) begin
+ if(RST)
+ count <= 0;
+ else begin
+ count <= count - 1'd1;
+ if(count == 0)
+ count <= COUNT_TO;
+ end
+ end
+ end
+
+ "FALLING": begin
+ always @(posedge CLK, negedge RST) begin
+ if(!RST)
+ count <= 0;
+ else begin
+ count <= count - 1'd1;
+ if(count == 0)
+ count <= COUNT_TO;
+ end
+ end
+ end
+
+ "BOTH": begin
+ initial begin
+ $display("Both-edge reset mode for GP_COUNT14 not implemented");
+ $finish;
+ end
+ end
+
+ "LEVEL": begin
+ always @(posedge CLK, posedge RST) begin
+ if(RST)
+ count <= 0;
+
+ else begin
+ count <= count - 1'd1;
+ if(count == 0)
+ count <= COUNT_TO;
+ end
+ end
+ end
+
+ default: begin
+ initial begin
+ $display("Invalid RESET_MODE on GP_COUNT14");
+ $finish;
+ end
+ end
+
+ endcase
+ endgenerate
+
+endmodule
+
+module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
+ input UP, input KEEP, output reg[7:0] POUT);
+
+ parameter RESET_MODE = "RISING";
+ parameter RESET_VALUE = "ZERO";
+
+ parameter COUNT_TO = 14'h1;
+ parameter CLKIN_DIVIDE = 1;
+
+ initial begin
+ if(CLKIN_DIVIDE != 1) begin
+ $display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
+ $finish;
+ end
+ end
+
+ reg[13:0] count = COUNT_TO;
+
+ //Combinatorially output underflow flag whenever we wrap low
+ always @(*) begin
+ if(UP)
+ OUT <= (count == 14'h3fff);
+ else
+ OUT <= (count == 14'h0);
+ POUT <= count[7:0];
+ end
+
+ //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
+ //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
+ generate
+ case(RESET_MODE)
+
+ "RISING": begin
+ always @(posedge CLK, posedge RST) begin
+
+ //Resets
+ if(RST) begin
+ if(RESET_VALUE == "ZERO")
+ count <= 0;
+ else
+ count <= COUNT_TO;
+ end
+
+ else if(KEEP) begin
+ end
+ else if(UP) begin
+ count <= count + 1'd1;
+ if(count == 14'h3fff)
+ count <= COUNT_TO;
+ end
+ else begin
+ count <= count - 1'd1;
+
+ if(count == 0)
+ count <= COUNT_TO;
+ end
+
+ end
+ end
+
+ "FALLING": begin
+ always @(posedge CLK, negedge RST) begin
+
+ //Resets
+ if(!RST) begin
+ if(RESET_VALUE == "ZERO")
+ count <= 0;
+ else
+ count <= COUNT_TO;
+ end
+
+ else if(KEEP) begin
+ end
+ else if(UP) begin
+ count <= count + 1'd1;
+ if(count == 14'h3fff)
+ count <= COUNT_TO;
+ end
+ else begin
+ count <= count - 1'd1;
+
+ if(count == 0)
+ count <= COUNT_TO;
+ end
+
+ end
+ end
+
+ "BOTH": begin
+ initial begin
+ $display("Both-edge reset mode for GP_COUNT14_ADV not implemented");
+ $finish;
+ end
+ end
+
+ "LEVEL": begin
+ always @(posedge CLK, posedge RST) begin
+
+ //Resets
+ if(RST) begin
+ if(RESET_VALUE == "ZERO")
+ count <= 0;
+ else
+ count <= COUNT_TO;
+ end
+
+ else begin
+
+ if(KEEP) begin
+ end
+ else if(UP) begin
+ count <= count + 1'd1;
+ if(count == 14'h3fff)
+ count <= COUNT_TO;
+ end
+ else begin
+ count <= count - 1'd1;
+
+ if(count == 0)
+ count <= COUNT_TO;
+ end
+
+ end
+
+ end
+ end
+
+ default: begin
+ initial begin
+ $display("Invalid RESET_MODE on GP_COUNT14_ADV");
+ $finish;
+ end
+ end
+
+ endcase
+ endgenerate
+
+endmodule
+
+module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
+ input UP, input KEEP, output reg[7:0] POUT);
+
+ parameter RESET_MODE = "RISING";
+ parameter RESET_VALUE = "ZERO";
+
+ parameter COUNT_TO = 8'h1;
+ parameter CLKIN_DIVIDE = 1;
+
+ reg[7:0] count = COUNT_TO;
+
+ initial begin
+ if(CLKIN_DIVIDE != 1) begin
+ $display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
+ $finish;
+ end
+ end
+
+ //Combinatorially output underflow flag whenever we wrap low
+ always @(*) begin
+ if(UP)
+ OUT <= (count == 8'hff);
+ else
+ OUT <= (count == 8'h0);
+ POUT <= count;
+ end
+
+ //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
+ //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
+ generate
+ case(RESET_MODE)
+
+ "RISING": begin
+ always @(posedge CLK, posedge RST) begin
+
+ //Resets
+ if(RST) begin
+ if(RESET_VALUE == "ZERO")
+ count <= 0;
+ else
+ count <= COUNT_TO;
+ end
+
+ //Main counter
+ else if(KEEP) begin
+ end
+ else if(UP) begin
+ count <= count + 1'd1;
+ if(count == 8'hff)
+ count <= COUNT_TO;
+ end
+ else begin
+ count <= count - 1'd1;
+
+ if(count == 0)
+ count <= COUNT_TO;
+ end
+
+ end
+ end
+
+ "FALLING": begin
+ always @(posedge CLK, negedge RST) begin
+
+ //Resets
+ if(!RST) begin
+ if(RESET_VALUE == "ZERO")
+ count <= 0;
+ else
+ count <= COUNT_TO;
+ end
+
+ //Main counter
+ else if(KEEP) begin
+ end
+ else if(UP) begin
+ count <= count + 1'd1;
+ if(count == 8'hff)
+ count <= COUNT_TO;
+ end
+ else begin
+ count <= count - 1'd1;
+
+ if(count == 0)
+ count <= COUNT_TO;
+ end
+
+ end
+ end
+
+ "BOTH": begin
+ initial begin
+ $display("Both-edge reset mode for GP_COUNT8_ADV not implemented");
+ $finish;
+ end
+ end
+
+ "LEVEL": begin
+ always @(posedge CLK, posedge RST) begin
+
+ //Resets
+ if(RST) begin
+ if(RESET_VALUE == "ZERO")
+ count <= 0;
+ else
+ count <= COUNT_TO;
+ end
+
+ else begin
+
+ if(KEEP) begin
+ end
+ else if(UP) begin
+ count <= count + 1'd1;
+ if(count == 8'hff)
+ count <= COUNT_TO;
+ end
+ else begin
+ count <= count - 1'd1;
+
+ if(count == 0)
+ count <= COUNT_TO;
+ end
+ end
+
+ end
+ end
+
+ default: begin
+ initial begin
+ $display("Invalid RESET_MODE on GP_COUNT8_ADV");
+ $finish;
+ end
+ end
+
+ endcase
+ endgenerate
+
+endmodule
+
+module GP_COUNT8(
+ input wire CLK,
+ input wire RST,
+ output reg OUT,
+ output reg[7:0] POUT);
+
+ parameter RESET_MODE = "RISING";
+
+ parameter COUNT_TO = 8'h1;
+ parameter CLKIN_DIVIDE = 1;
+
+ initial begin
+ if(CLKIN_DIVIDE != 1) begin
+ $display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
+ $finish;
+ end
+ end
+
+ reg[7:0] count = COUNT_TO;
+
+ //Combinatorially output underflow flag whenever we wrap low
+ always @(*) begin
+ OUT <= (count == 8'h0);
+ POUT <= count;
+ end
+
+ //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
+ //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
+ generate
+ case(RESET_MODE)
+
+ "RISING": begin
+ always @(posedge CLK, posedge RST) begin
+ if(RST)
+ count <= 0;
+ else begin
+ count <= count - 1'd1;
+ if(count == 0)
+ count <= COUNT_TO;
+ end
+ end
+ end
+
+ "FALLING": begin
+ always @(posedge CLK, negedge RST) begin
+ if(!RST)
+ count <= 0;
+ else begin
+ count <= count - 1'd1;
+ if(count == 0)
+ count <= COUNT_TO;
+ end
+ end
+ end
+
+ "BOTH": begin
+ initial begin
+ $display("Both-edge reset mode for GP_COUNT8 not implemented");
+ $finish;
+ end
+ end
+
+ "LEVEL": begin
+ always @(posedge CLK, posedge RST) begin
+ if(RST)
+ count <= 0;
+
+ else begin
+ count <= count - 1'd1;
+ if(count == 0)
+ count <= COUNT_TO;
+ end
+ end
+ end
+
+ default: begin
+ initial begin
+ $display("Invalid RESET_MODE on GP_COUNT8");
+ $finish;
+ end
+ end
+
+ endcase
+ endgenerate
+
+endmodule
+
+module GP_DCMPREF(output reg[7:0]OUT);
+ parameter[7:0] REF_VAL = 8'h00;
+ initial OUT = REF_VAL;
+endmodule
+
+module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
+
+ always @(*) begin
+ case(SEL)
+ 2'd00: begin
+ OUTA <= IN0;
+ OUTB <= IN3;
+ end
+
+ 2'd01: begin
+ OUTA <= IN1;
+ OUTB <= IN2;
+ end
+
+ 2'd02: begin
+ OUTA <= IN2;
+ OUTB <= IN1;
+ end
+
+ 2'd03: begin
+ OUTA <= IN3;
+ OUTB <= IN0;
+ end
+
+ endcase
+ end
+endmodule
+
+module GP_DELAY(input IN, output reg OUT);
+
+ parameter DELAY_STEPS = 1;
+ parameter GLITCH_FILTER = 0;
+
+ initial OUT = 0;
+
+ generate
+
+ if(GLITCH_FILTER) begin
+ initial begin
+ $display("ERROR: GP_DELAY glitch filter mode not implemented");
+ $finish;
+ end
+ end
+
+ //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
+ //Change simulation-mode delay depending on global Vdd range (how to specify this?)
+ always @(*) begin
+ case(DELAY_STEPS)
+ 1: #166 OUT = IN;
+ 2: #318 OUT = IN;
+ 2: #471 OUT = IN;
+ 3: #622 OUT = IN;
+ default: begin
+ $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
+ $finish;
+ end
+ endcase
+ end
+
+ endgenerate
+
+endmodule
+
+module GP_DFF(input D, CLK, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ initial Q = INIT;
+ always @(posedge CLK) begin
+ Q <= D;
+ end
+endmodule
+
+module GP_DFFI(input D, CLK, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ initial nQ = INIT;
+ always @(posedge CLK) begin
+ nQ <= ~D;
+ end
+endmodule
+
+module GP_DFFR(input D, CLK, nRST, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ initial Q = INIT;
+ always @(posedge CLK, negedge nRST) begin
+ if (!nRST)
+ Q <= 1'b0;
+ else
+ Q <= D;
+ end
+endmodule
+
+module GP_DFFRI(input D, CLK, nRST, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ initial nQ = INIT;
+ always @(posedge CLK, negedge nRST) begin
+ if (!nRST)
+ nQ <= 1'b1;
+ else
+ nQ <= ~D;
+ end
+endmodule
+
+module GP_DFFS(input D, CLK, nSET, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ initial Q = INIT;
+ always @(posedge CLK, negedge nSET) begin
+ if (!nSET)
+ Q <= 1'b1;
+ else
+ Q <= D;
+ end
+endmodule
+
+module GP_DFFSI(input D, CLK, nSET, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ initial nQ = INIT;
+ always @(posedge CLK, negedge nSET) begin
+ if (!nSET)
+ nQ <= 1'b0;
+ else
+ nQ <= ~D;
+ end
+endmodule
+
+module GP_DFFSR(input D, CLK, nSR, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ parameter [0:0] SRMODE = 1'bx;
+ initial Q = INIT;
+ always @(posedge CLK, negedge nSR) begin
+ if (!nSR)
+ Q <= SRMODE;
+ else
+ Q <= D;
+ end
+endmodule
+
+module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ parameter [0:0] SRMODE = 1'bx;
+ initial nQ = INIT;
+ always @(posedge CLK, negedge nSR) begin
+ if (!nSR)
+ nQ <= ~SRMODE;
+ else
+ nQ <= ~D;
+ end
+endmodule
+
+module GP_DLATCH(input D, input nCLK, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ initial Q = INIT;
+ always @(*) begin
+ if(!nCLK)
+ Q <= D;
+ end
+endmodule
+
+module GP_DLATCHI(input D, input nCLK, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ initial nQ = INIT;
+ always @(*) begin
+ if(!nCLK)
+ nQ <= ~D;
+ end
+endmodule
+
+module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ initial Q = INIT;
+ always @(*) begin
+ if(!nRST)
+ Q <= 1'b0;
+ else if(!nCLK)
+ Q <= D;
+ end
+endmodule
+
+module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ initial nQ = INIT;
+ always @(*) begin
+ if(!nRST)
+ nQ <= 1'b1;
+ else if(!nCLK)
+ nQ <= ~D;
+ end
+endmodule
+
+module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ initial Q = INIT;
+ always @(*) begin
+ if(!nSET)
+ Q <= 1'b1;
+ else if(!nCLK)
+ Q <= D;
+ end
+endmodule
+
+module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ initial nQ = INIT;
+ always @(*) begin
+ if(!nSET)
+ nQ <= 1'b0;
+ else if(!nCLK)
+ nQ <= ~D;
+ end
+endmodule
+
+module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
+ parameter [0:0] INIT = 1'bx;
+ parameter[0:0] SRMODE = 1'bx;
+ initial Q = INIT;
+ always @(*) begin
+ if(!nSR)
+ Q <= SRMODE;
+ else if(!nCLK)
+ Q <= D;
+ end
+endmodule
+
+module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
+ parameter [0:0] INIT = 1'bx;
+ parameter[0:0] SRMODE = 1'bx;
+ initial nQ = INIT;
+ always @(*) begin
+ if(!nSR)
+ nQ <= ~SRMODE;
+ else if(!nCLK)
+ nQ <= ~D;
+ end
+endmodule
+
+module GP_IBUF(input IN, output OUT);
+ assign OUT = IN;
+endmodule
+
+module GP_IOBUF(input IN, input OE, output OUT, inout IO);
+ assign OUT = IO;
+ assign IO = OE ? IN : 1'bz;
+endmodule
+
+module GP_INV(input IN, output OUT);
+ assign OUT = ~IN;
+endmodule
+
+module GP_OBUF(input IN, output OUT);
+ assign OUT = IN;
+endmodule
+
+module GP_OBUFT(input IN, input OE, output OUT);
+ assign OUT = OE ? IN : 1'bz;
+endmodule
+
+module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
+ initial OUT = 0;
+ parameter PATTERN_DATA = 16'h0;
+ parameter PATTERN_LEN = 5'd16;
+
+ localparam COUNT_MAX = PATTERN_LEN - 1'h1;
+
+ reg[3:0] count = 0;
+ always @(posedge CLK, negedge nRST) begin
+
+ if(!nRST)
+ count <= 0;
+
+ else begin
+ count <= count - 1'h1;
+ if(count == 0)
+ count <= COUNT_MAX;
+ end
+ end
+
+ always @(*)
+ OUT = PATTERN_DATA[count];
+
+endmodule
+
+module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
+
+ parameter OUTA_TAP = 1;
+ parameter OUTA_INVERT = 0;
+ parameter OUTB_TAP = 1;
+
+ reg[15:0] shreg = 0;
+
+ always @(posedge CLK, negedge nRST) begin
+
+ if(!nRST)
+ shreg = 0;
+
+ else
+ shreg <= {shreg[14:0], IN};
+
+ end
+
+ assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
+ assign OUTB = shreg[OUTB_TAP - 1];
+
+endmodule
+
+module GP_VDD(output OUT);
+ assign OUT = 1;
+endmodule
+
+module GP_VSS(output OUT);
+ assign OUT = 0;
+endmodule
diff --git a/techlibs/greenpak4/cells_sim_wip.v b/techlibs/greenpak4/cells_sim_wip.v
new file mode 100644
index 00000000..5261b12d
--- /dev/null
+++ b/techlibs/greenpak4/cells_sim_wip.v
@@ -0,0 +1,136 @@
+
+//Cells still in this file have INCOMPLETE simulation models, need to finish them
+
+module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg GREATER, output reg EQUAL);
+ parameter PWRDN_SYNC = 1'b0;
+ parameter CLK_EDGE = "RISING";
+ parameter GREATER_OR_EQUAL = 1'b0;
+
+ //TODO implement power-down mode
+
+ initial GREATER = 0;
+ initial EQUAL = 0;
+
+ wire clk_minv = (CLK_EDGE == "RISING") ? CLK : ~CLK;
+ always @(posedge clk_minv) begin
+ if(GREATER_OR_EQUAL)
+ GREATER <= (INP >= INN);
+ else
+ GREATER <= (INP > INN);
+
+ EQUAL <= (INP == INN);
+ end
+
+endmodule
+
+module GP_EDGEDET(input IN, output reg OUT);
+
+ parameter EDGE_DIRECTION = "RISING";
+ parameter DELAY_STEPS = 1;
+ parameter GLITCH_FILTER = 0;
+
+ //not implemented for simulation
+
+endmodule
+
+module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
+
+ parameter PWRDN_EN = 0;
+ parameter AUTO_PWRDN = 0;
+ parameter HARDIP_DIV = 1;
+ parameter FABRIC_DIV = 1;
+ parameter OSC_FREQ = "25k";
+
+ initial CLKOUT_HARDIP = 0;
+ initial CLKOUT_FABRIC = 0;
+
+ //output dividers not implemented for simulation
+ //auto powerdown not implemented for simulation
+
+ always begin
+ if(PWRDN) begin
+ CLKOUT_HARDIP = 0;
+ CLKOUT_FABRIC = 0;
+ end
+ else begin
+
+ if(OSC_FREQ == "25k") begin
+ //half period of 25 kHz
+ #20000;
+ end
+
+ else begin
+ //half period of 2 MHz
+ #250;
+ end
+
+ CLKOUT_HARDIP = ~CLKOUT_HARDIP;
+ CLKOUT_FABRIC = ~CLKOUT_FABRIC;
+ end
+ end
+
+endmodule
+
+module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
+
+ parameter PWRDN_EN = 0;
+ parameter AUTO_PWRDN = 0;
+ parameter HARDIP_DIV = 1;
+ parameter FABRIC_DIV = 1;
+
+ initial CLKOUT_HARDIP = 0;
+ initial CLKOUT_FABRIC = 0;
+
+ //output dividers not implemented for simulation
+ //auto powerdown not implemented for simulation
+
+ always begin
+ if(PWRDN) begin
+ CLKOUT_HARDIP = 0;
+ CLKOUT_FABRIC = 0;
+ end
+ else begin
+ //half period of 27 MHz
+ #18.518;
+ CLKOUT_HARDIP = ~CLKOUT_HARDIP;
+ CLKOUT_FABRIC = ~CLKOUT_FABRIC;
+ end
+ end
+
+endmodule
+
+module GP_SPI(
+ input SCK,
+ inout SDAT,
+ input CSN,
+ input[7:0] TXD_HIGH,
+ input[7:0] TXD_LOW,
+ output reg[7:0] RXD_HIGH,
+ output reg[7:0] RXD_LOW,
+ output reg INT);
+
+ initial RXD_HIGH = 0;
+ initial RXD_LOW = 0;
+ initial INT = 0;
+
+ parameter DATA_WIDTH = 8; //byte or word width
+ parameter SPI_CPHA = 0; //SPI clock phase
+ parameter SPI_CPOL = 0; //SPI clock polarity
+ parameter DIRECTION = "INPUT"; //SPI data direction (either input to chip or output to host)
+ //parallel output to fabric not yet implemented
+
+ //TODO: write sim model
+ //TODO: SPI SDIO control... can we use ADC output while SPI is input??
+ //TODO: clock sync
+
+endmodule
+
+//keep constraint needed to prevent optimization since we have no outputs
+(* keep *)
+module GP_SYSRESET(input RST);
+ parameter RESET_MODE = "EDGE";
+ parameter EDGE_SPEED = 4;
+
+ //cannot simulate whole system reset
+
+endmodule
diff --git a/techlibs/greenpak4/greenpak4_counters.cc b/techlibs/greenpak4/greenpak4_counters.cc
deleted file mode 100644
index 998bb73b..00000000
--- a/techlibs/greenpak4/greenpak4_counters.cc
+++ /dev/null
@@ -1,442 +0,0 @@
-/*
- * yosys -- Yosys Open SYnthesis Suite
- *
- * Copyright (C) 2016 Clifford Wolf <clifford@clifford.at>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "kernel/yosys.h"
-#include "kernel/sigtools.h"
-#include "kernel/modtools.h"
-
-USING_YOSYS_NAMESPACE
-PRIVATE_NAMESPACE_BEGIN
-
-//get the list of cells hooked up to at least one bit of a given net
-pool<Cell*> get_other_cells(const RTLIL::SigSpec& port, ModIndex& index, Cell* src)
-{
- pool<Cell*> rval;
- for(auto b : port)
- {
- pool<ModIndex::PortInfo> ports = index.query_ports(b);
- for(auto x : ports)
- {
- if(x.cell == src)
- continue;
- rval.insert(x.cell);
- }
- }
- return rval;
-}
-
-//return true if there is a full-width bus connection from cell a port ap to cell b port bp
-//if other_conns_allowed is false, then we require a strict point to point connection (no other links)
-bool is_full_bus(
- const RTLIL::SigSpec& sig,
- ModIndex& index,
- Cell* a,
- RTLIL::IdString ap,
- Cell* b,
- RTLIL::IdString bp,
- bool other_conns_allowed = false)
-{
- for(auto s : sig)
- {
- pool<ModIndex::PortInfo> ports = index.query_ports(s);
- bool found_a = false;
- bool found_b = false;
- for(auto x : ports)
- {
- if( (x.cell == a) && (x.port == ap) )
- found_a = true;
- else if( (x.cell == b) && (x.port == bp) )
- found_b = true;
- else if(!other_conns_allowed)
- return false;
- }
-
- if( (!found_a) || (!found_b) )
- return false;
- }
-
- return true;
-}
-
-//return true if the signal connects to one port only (nothing on the other end)
-bool is_unconnected(const RTLIL::SigSpec& port, ModIndex& index)
-{
- for(auto b : port)
- {
- pool<ModIndex::PortInfo> ports = index.query_ports(b);
- if(ports.size() > 1)
- return false;
- }
-
- return true;
-}
-
-struct CounterExtraction
-{
- int width; //counter width
- RTLIL::Wire* rwire; //the register output
- bool has_reset; //true if we have a reset
- RTLIL::SigSpec rst; //reset pin
- int count_value; //value we count from
- RTLIL::SigSpec clk; //clock signal
- RTLIL::SigSpec outsig; //counter output signal
- RTLIL::Cell* count_mux; //counter mux
- RTLIL::Cell* count_reg; //counter register
- RTLIL::Cell* underflow_inv; //inverter reduction for output-underflow detect
-};
-
-//attempt to extract a counter centered on the given cell
-int greenpak4_counters_tryextract(ModIndex& index, Cell *cell, CounterExtraction& extract)
-{
- SigMap& sigmap = index.sigmap;
-
- //GreenPak does not support counters larger than 14 bits so immediately skip anything bigger
- int a_width = cell->getParam("\\A_WIDTH").as_int();
- extract.width = a_width;
- if(a_width > 14)
- return 1;
-
- //Second input must be a single bit
- int b_width = cell->getParam("\\B_WIDTH").as_int();
- if(b_width != 1)
- return 2;
-
- //Both inputs must be unsigned, so don't extract anything with a signed input
- bool a_sign = cell->getParam("\\A_SIGNED").as_bool();
- bool b_sign = cell->getParam("\\B_SIGNED").as_bool();
- if(a_sign || b_sign)
- return 3;
-
- //To be a counter, one input of the ALU must be a constant 1
- //TODO: can A or B be swapped in synthesized RTL or is B always the 1?
- const RTLIL::SigSpec b_port = sigmap(cell->getPort("\\B"));
- if(!b_port.is_fully_const() || (b_port.as_int() != 1) )
- return 4;
-
- //BI and CI must be constant 1 as well
- const RTLIL::SigSpec bi_port = sigmap(cell->getPort("\\BI"));
- if(!bi_port.is_fully_const() || (bi_port.as_int() != 1) )
- return 5;
- const RTLIL::SigSpec ci_port = sigmap(cell->getPort("\\CI"));
- if(!ci_port.is_fully_const() || (ci_port.as_int() != 1) )
- return 6;
-
- //CO and X must be unconnected (exactly one connection to each port)
- if(!is_unconnected(sigmap(cell->getPort("\\CO")), index))
- return 7;
- if(!is_unconnected(sigmap(cell->getPort("\\X")), index))
- return 8;
-
- //Y must have exactly one connection, and it has to be a $mux cell.
- //We must have a direct bus connection from our Y to their A.
- const RTLIL::SigSpec aluy = sigmap(cell->getPort("\\Y"));
- pool<Cell*> y_loads = get_other_cells(aluy, index, cell);
- if(y_loads.size() != 1)
- return 9;
- Cell* count_mux = *y_loads.begin();
- extract.count_mux = count_mux;
- if(count_mux->type != "$mux")
- return 10;
- if(!is_full_bus(aluy, index, cell, "\\Y", count_mux, "\\A"))
- return 11;
-
- //B connection of the mux is our underflow value
- const RTLIL::SigSpec underflow = sigmap(count_mux->getPort("\\B"));
- if(!underflow.is_fully_const())
- return 12;
- extract.count_value = underflow.as_int();
-
- //S connection of the mux must come from an inverter (need not be the only load)
- const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort("\\S"));
- extract.outsig = muxsel;
- pool<Cell*> muxsel_conns = get_other_cells(muxsel, index, count_mux);
- Cell* underflow_inv = NULL;
- for(auto c : muxsel_conns)
- {
- if(c->type != "$logic_not")
- continue;
- if(!is_full_bus(muxsel, index, c, "\\Y", count_mux, "\\S", true))
- continue;
-
- underflow_inv = c;
- break;
- }
- if(underflow_inv == NULL)
- return 13;
- extract.underflow_inv = underflow_inv;
-
- //Y connection of the mux must have exactly one load, the counter's internal register
- const RTLIL::SigSpec muxy = sigmap(count_mux->getPort("\\Y"));
- pool<Cell*> muxy_loads = get_other_cells(muxy, index, count_mux);
- if(muxy_loads.size() != 1)
- return 14;
- Cell* count_reg = *muxy_loads.begin();
- extract.count_reg = count_reg;
- if(count_reg->type == "$dff")
- extract.has_reset = false;
- else if(count_reg->type == "$adff")
- {
- extract.has_reset = true;
-
- //Verify ARST_VALUE is zero and ARST_POLARITY is 1
- //TODO: infer an inverter to make it 1 if necessary, so we can support negative level resets?
- if(count_reg->getParam("\\ARST_POLARITY").as_int() != 1)
- return 22;
- if(count_reg->getParam("\\ARST_VALUE").as_int() != 0)
- return 23;
-
- //Save the reset
- extract.rst = sigmap(count_reg->getPort("\\ARST"));
- }
- //TODO: support synchronous reset
- else
- return 15;
- if(!is_full_bus(muxy, index, count_mux, "\\Y", count_reg, "\\D"))
- return 16;
-
- //TODO: Verify count_reg CLK_POLARITY is 1
-
- //Register output must have exactly two loads, the inverter and ALU
- const RTLIL::SigSpec cnout = sigmap(count_reg->getPort("\\Q"));
- pool<Cell*> cnout_loads = get_other_cells(cnout, index, count_reg);
- if(cnout_loads.size() != 2)
- return 17;
- if(!is_full_bus(cnout, index, count_reg, "\\Q", underflow_inv, "\\A", true))
- return 18;
- if(!is_full_bus(cnout, index, count_reg, "\\Q", cell, "\\A", true))
- return 19;
-
- //Look up the clock from the register
- extract.clk = sigmap(count_reg->getPort("\\CLK"));
-
- //Register output net must have an INIT attribute equal to the count value
- extract.rwire = cnout.as_wire();
- if(extract.rwire->attributes.find("\\init") == extract.rwire->attributes.end())
- return 20;
- int rinit = extract.rwire->attributes["\\init"].as_int();
- if(rinit != extract.count_value)
- return 21;
-
- return 0;
-}
-
-void greenpak4_counters_worker(
- ModIndex& index,
- Cell *cell,
- unsigned int& total_counters,
- pool<Cell*>& cells_to_remove)
-{
- SigMap& sigmap = index.sigmap;
-
- //Core of the counter must be an ALU
- if (cell->type != "$alu")
- return;
-
- //A input is the count value. Check if it has COUNT_EXTRACT set.
- //If it's not a wire, don't even try
- auto port = sigmap(cell->getPort("\\A"));
- if(!port.is_wire())
- return;
- RTLIL::Wire* a_wire = port.as_wire();
- bool force_extract = false;
- bool never_extract = false;
- string count_reg_src = a_wire->attributes["\\src"].decode_string().c_str();
- if(a_wire->attributes.find("\\COUNT_EXTRACT") != a_wire->attributes.end())
- {
- pool<string> sa = a_wire->get_strpool_attribute("\\COUNT_EXTRACT");
- string extract_value;
- if(sa.size() >= 1)
- {
- extract_value = *sa.begin();
- log(" Signal %s declared at %s has COUNT_EXTRACT = %s\n",
- log_id(a_wire),
- count_reg_src.c_str(),
- extract_value.c_str());
-
- if(extract_value == "FORCE")
- force_extract = true;
- else if(extract_value == "NO")
- never_extract = true;
- else if(extract_value == "AUTO")
- {} //default
- else
- log_error(" Illegal COUNT_EXTRACT value %s (must be one of FORCE, NO, AUTO)\n",
- extract_value.c_str());
- }
- }
-
- //If we're explicitly told not to extract, don't infer a counter
- if(never_extract)
- return;
-
- //Attempt to extract a counter
- CounterExtraction extract;
- int reason = greenpak4_counters_tryextract(index, cell, extract);
-
- //Nonzero code - we could not find a matchable counter.
- //Do nothing, unless extraction was forced in which case give an error
- if(reason != 0)
- {
- static const char* reasons[24]=
- {
- "no problem", //0
- "counter is larger than 14 bits", //1
- "counter does not count by one", //2
- "counter uses signed math", //3
- "counter does not count by one", //4
- "ALU is not a subtractor", //5
- "ALU is not a subtractor", //6
- "ALU ports used outside counter", //7
- "ALU ports used outside counter", //8
- "ALU output used outside counter", //9
- "ALU output is not a mux", //10
- "ALU output is not full bus", //11
- "Underflow value is not constant", //12
- "No underflow detector found", //13
- "Mux output is used outside counter", //14
- "Counter reg is not DFF/ADFF", //15
- "Counter input is not full bus", //16
- "Count register is used outside counter", //17
- "Register output is not full bus", //18
- "Register output is not full bus", //19
- "No init value found", //20
- "Underflow value is not equal to init value", //21
- "Reset polarity is not positive", //22
- "Reset is not to zero" //23
- };
-
- if(force_extract)
- {
- log_error(
- "Counter extraction is set to FORCE on register %s, but a counter could not be inferred (%s)\n",
- log_id(a_wire),
- reasons[reason]);
- }
- return;
- }
-
- //Figure out the final cell type based on the counter size
- string celltype = "\\GP_COUNT8";
- if(extract.width > 8)
- celltype = "\\GP_COUNT14";
-
- //Log it
- total_counters ++;
- string reset_type = "non-resettable";
- if(extract.has_reset)
- {
- //TODO: support other kind of reset
- reset_type = "async resettable";
- }
- log(" Found %d-bit %s down counter (from %d) for register %s declared at %s\n",
- extract.width,
- reset_type.c_str(),
- extract.count_value,
- log_id(extract.rwire->name),
- count_reg_src.c_str());
-
- //Wipe all of the old connections to the ALU
- cell->unsetPort("\\A");
- cell->unsetPort("\\B");
- cell->unsetPort("\\BI");
- cell->unsetPort("\\CI");
- cell->unsetPort("\\CO");
- cell->unsetPort("\\X");
- cell->unsetPort("\\Y");
- cell->unsetParam("\\A_SIGNED");
- cell->unsetParam("\\A_WIDTH");
- cell->unsetParam("\\B_SIGNED");
- cell->unsetParam("\\B_WIDTH");
- cell->unsetParam("\\Y_WIDTH");
-
- //Change the cell type
- cell->type = celltype;
-
- //Hook up resets
- if(extract.has_reset)
- {
- //TODO: support other kinds of reset
- cell->setParam("\\RESET_MODE", RTLIL::Const("LEVEL"));
- cell->setPort("\\RST", extract.rst);
- }
- else
- {
- cell->setParam("\\RESET_MODE", RTLIL::Const("RISING"));
- cell->setPort("\\RST", RTLIL::SigSpec(false));
- }
-
- //Hook up other stuff
- cell->setParam("\\CLKIN_DIVIDE", RTLIL::Const(1));
- cell->setParam("\\COUNT_TO", RTLIL::Const(extract.count_value));
-
- cell->setPort("\\CLK", extract.clk);
- cell->setPort("\\OUT", extract.outsig);
-
- //Delete the cells we've replaced (let opt_clean handle deleting the now-redundant wires)
- cells_to_remove.insert(extract.count_mux);
- cells_to_remove.insert(extract.count_reg);
- cells_to_remove.insert(extract.underflow_inv);
-}
-
-struct Greenpak4CountersPass : public Pass {
- Greenpak4CountersPass() : Pass("greenpak4_counters", "Extract GreenPak4 counter cells") { }
- virtual void help()
- {
- // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
- log("\n");
- log(" greenpak4_counters [options] [selection]\n");
- log("\n");
- log("This pass converts non-resettable or async resettable down counters to GreenPak4\n");
- log("counter cells (All other GreenPak4 counter modes must be instantiated manually.)\n");
- log("\n");
- }
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
- {
- log_header(design, "Executing GREENPAK4_COUNTERS pass (mapping counters to hard IP blocks).\n");
-
- size_t argidx;
- for (argidx = 1; argidx < args.size(); argidx++)
- {
- // if (args[argidx] == "-v") {
- // continue;
- // }
- break;
- }
- extra_args(args, argidx, design);
-
- //Extract all of the counters we could find
- unsigned int total_counters = 0;
- for (auto module : design->selected_modules())
- {
- pool<Cell*> cells_to_remove;
-
- ModIndex index(module);
- for (auto cell : module->selected_cells())
- greenpak4_counters_worker(index, cell, total_counters, cells_to_remove);
-
- for(auto cell : cells_to_remove)
- module->remove(cell);
- }
-
- if(total_counters)
- log("Extracted %u counters\n", total_counters);
- }
-} Greenpak4CountersPass;
-
-PRIVATE_NAMESPACE_END
diff --git a/techlibs/greenpak4/greenpak4_dffinv.cc b/techlibs/greenpak4/greenpak4_dffinv.cc
index ff63958e..d57e978a 100644
--- a/techlibs/greenpak4/greenpak4_dffinv.cc
+++ b/techlibs/greenpak4/greenpak4_dffinv.cc
@@ -26,6 +26,7 @@ PRIVATE_NAMESPACE_BEGIN
void invert_gp_dff(Cell *cell, bool invert_input)
{
string cell_type = cell->type.str();
+ bool cell_type_latch = cell_type.find("LATCH") != string::npos;
bool cell_type_i = cell_type.find('I') != string::npos;
bool cell_type_r = cell_type.find('R') != string::npos;
bool cell_type_s = cell_type.find('S') != string::npos;
@@ -79,25 +80,28 @@ void invert_gp_dff(Cell *cell, bool invert_input)
cell_type_i = true;
}
- cell->type = stringf("\\GP_DFF%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
+ if(cell_type_latch)
+ cell->type = stringf("\\GP_DLATCH%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
+ else
+ cell->type = stringf("\\GP_DFF%s%s%s", cell_type_s ? "S" : "", cell_type_r ? "R" : "", cell_type_i ? "I" : "");
log("Merged %s inverter into cell %s.%s: %s -> %s\n", invert_input ? "input" : "output",
log_id(cell->module), log_id(cell), cell_type.c_str()+1, log_id(cell->type));
}
struct Greenpak4DffInvPass : public Pass {
- Greenpak4DffInvPass() : Pass("greenpak4_dffinv", "merge greenpak4 inverters and DFFs") { }
- virtual void help()
+ Greenpak4DffInvPass() : Pass("greenpak4_dffinv", "merge greenpak4 inverters and DFF/latches") { }
+ void help() YS_OVERRIDE
{
log("\n");
log(" greenpak4_dffinv [options] [selection]\n");
log("\n");
- log("Merge GP_INV cells with GP_DFF* cells.\n");
+ log("Merge GP_INV cells with GP_DFF* and GP_DLATCH* cells.\n");
log("\n");
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
- log_header(design, "Executing GREENPAK4_DFFINV pass (merge synchronous set/reset into FF cells).\n");
+ log_header(design, "Executing GREENPAK4_DFFINV pass (merge input/output inverters into FF/latch cells).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@@ -120,6 +124,15 @@ struct Greenpak4DffInvPass : public Pass {
gp_dff_types.insert("\\GP_DFFSR");
gp_dff_types.insert("\\GP_DFFSRI");
+ gp_dff_types.insert("\\GP_DLATCH");
+ gp_dff_types.insert("\\GP_DLATCHI");
+ gp_dff_types.insert("\\GP_DLATCHR");
+ gp_dff_types.insert("\\GP_DLATCHRI");
+ gp_dff_types.insert("\\GP_DLATCHS");
+ gp_dff_types.insert("\\GP_DLATCHSI");
+ gp_dff_types.insert("\\GP_DLATCHSR");
+ gp_dff_types.insert("\\GP_DLATCHSRI");
+
for (auto module : design->selected_modules())
{
SigMap sigmap(module);
diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc
index 10e2a149..b91d5273 100644
--- a/techlibs/greenpak4/synth_greenpak4.cc
+++ b/techlibs/greenpak4/synth_greenpak4.cc
@@ -29,13 +29,15 @@ struct SynthGreenPAK4Pass : public ScriptPass
{
SynthGreenPAK4Pass() : ScriptPass("synth_greenpak4", "synthesis for GreenPAK4 FPGAs") { }
- virtual void help() YS_OVERRIDE
+ void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" synth_greenpak4 [options]\n");
log("\n");
log("This command runs synthesis for GreenPAK4 FPGAs. This work is experimental.\n");
+ log("It is intended to be used with https://github.com/azonenberg/openfpga as the\n");
+ log("place-and-route.\n");
log("\n");
log(" -top <module>\n");
log(" use the specified module as top module (default='top')\n");
@@ -68,7 +70,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
string top_opt, part, json_file;
bool flatten, retime;
- virtual void clear_flags() YS_OVERRIDE
+ void clear_flags() YS_OVERRIDE
{
top_opt = "-auto-top";
part = "SLG46621V";
@@ -77,7 +79,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
retime = false;
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
string run_from, run_to;
clear_flags();
@@ -131,7 +133,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
log_pop();
}
- virtual void script() YS_OVERRIDE
+ void script() YS_OVERRIDE
{
if (check_label("begin"))
{
@@ -153,12 +155,13 @@ struct SynthGreenPAK4Pass : public ScriptPass
if (check_label("fine"))
{
- run("greenpak4_counters");
+ run("extract_counter -pout GP_DCMP,GP_DAC -maxwidth 14");
run("clean");
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("opt -undriven -fine");
run("techmap");
+ run("techmap -map +/greenpak4/cells_latch.v");
run("dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib");
run("opt -fast");
if (retime || help_mode)
@@ -201,8 +204,6 @@ struct SynthGreenPAK4Pass : public ScriptPass
if (!json_file.empty() || help_mode)
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
}
-
- log_pop();
}
} SynthGreenPAK4Pass;
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-06 05:21:47 +0000