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Diffstat (limited to 'techlibs/ice40/synth_ice40.cc')
-rw-r--r--techlibs/ice40/synth_ice40.cc210
1 files changed, 82 insertions, 128 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 92d53f4a..38a9cf9d 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -25,18 +25,11 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
-bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
+struct SynthIce40Pass : public ScriptPass
{
- if (label == run_from)
- active = true;
- if (label == run_to)
- active = false;
- return active;
-}
+ SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
-struct SynthIce40Pass : public Pass {
- SynthIce40Pass() : Pass("synth_ice40", "synthesis for iCE40 FPGAs") { }
- virtual void help()
+ virtual void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -77,73 +70,29 @@ struct SynthIce40Pass : public Pass {
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
+ help_script();
log("\n");
- log(" begin:\n");
- log(" read_verilog -lib +/ice40/cells_sim.v\n");
- log(" hierarchy -check -top <top>\n");
- log("\n");
- log(" flatten: (unless -noflatten)\n");
- log(" proc\n");
- log(" flatten\n");
- log(" tribuf -logic\n");
- log("\n");
- log(" coarse:\n");
- log(" synth -run coarse\n");
- log("\n");
- log(" bram: (skip if -nobram)\n");
- log(" memory_bram -rules +/ice40/brams.txt\n");
- log(" techmap -map +/ice40/brams_map.v\n");
- log("\n");
- log(" fine:\n");
- log(" opt -fast -mux_undef -undriven -fine\n");
- log(" memory_map\n");
- log(" opt -undriven -fine\n");
- log(" techmap -map +/techmap.v [-map +/ice40/arith_map.v]\n");
- log(" abc -dff (only if -retime)\n");
- log(" ice40_opt\n");
- log("\n");
- log(" map_ffs:\n");
- log(" dffsr2dff\n");
- log(" dff2dffe -direct-match $_DFF_*\n");
- log(" techmap -map +/ice40/cells_map.v\n");
- log(" opt_const -mux_undef\n");
- log(" simplemap\n");
- log(" ice40_ffinit\n");
- log(" ice40_ffssr\n");
- log(" ice40_opt -full\n");
- log("\n");
- log(" map_luts:\n");
- log(" abc (only if -abc2)\n");
- log(" ice40_opt (only if -abc2)\n");
- log(" abc -lut 4\n");
- log(" clean\n");
- log("\n");
- log(" map_cells:\n");
- log(" techmap -map +/ice40/cells_map.v\n");
- log(" clean\n");
- log("\n");
- log(" check:\n");
- log(" hierarchy -check\n");
- log(" stat\n");
- log(" check -noinit\n");
- log("\n");
- log(" blif:\n");
- log(" write_blif -gates -attr -param <file-name>\n");
- log("\n");
- log(" edif:\n");
- log(" write_edif <file-name>\n");
- log("\n");
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+
+ string top_opt, blif_file, edif_file;
+ bool nocarry, nobram, flatten, retime, abc2;
+
+ virtual void clear_flags() YS_OVERRIDE
+ {
+ top_opt = "-auto-top";
+ blif_file = "";
+ edif_file = "";
+ nocarry = false;
+ nobram = false;
+ flatten = true;
+ retime = false;
+ abc2 = false;
+ }
+
+ virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
- std::string top_opt = "-auto-top";
- std::string run_from, run_to;
- std::string blif_file, edif_file;
- bool nocarry = false;
- bool nobram = false;
- bool flatten = true;
- bool retime = false;
- bool abc2 = false;
+ string run_from, run_to;
+ clear_flags();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@@ -199,97 +148,102 @@ struct SynthIce40Pass : public Pass {
if (!design->full_selection())
log_cmd_error("This comannd only operates on fully selected designs!\n");
- bool active = run_from.empty();
-
- log_header("Executing SYNTH_ICE40 pass.\n");
+ log_header(design, "Executing SYNTH_ICE40 pass.\n");
log_push();
- if (check_label(active, run_from, run_to, "begin"))
+ run_script(design, run_from, run_to);
+
+ log_pop();
+ }
+
+ virtual void script() YS_OVERRIDE
+ {
+ if (check_label("begin"))
{
- Pass::call(design, "read_verilog -lib +/ice40/cells_sim.v");
- Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str()));
+ run("read_verilog -lib +/ice40/cells_sim.v");
+ run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
}
- if (flatten && check_label(active, run_from, run_to, "flatten"))
+ if (flatten && check_label("flatten", "(unless -noflatten)"))
{
- Pass::call(design, "proc");
- Pass::call(design, "flatten");
- Pass::call(design, "tribuf -logic");
+ run("proc");
+ run("flatten");
+ run("tribuf -logic");
+ run("deminout");
}
- if (check_label(active, run_from, run_to, "coarse"))
+ if (check_label("coarse"))
{
- Pass::call(design, "synth -run coarse");
+ run("synth -run coarse");
}
- if (!nobram && check_label(active, run_from, run_to, "bram"))
+ if (!nobram && check_label("bram", "(skip if -nobram)"))
{
- Pass::call(design, "memory_bram -rules +/ice40/brams.txt");
- Pass::call(design, "techmap -map +/ice40/brams_map.v");
+ run("memory_bram -rules +/ice40/brams.txt");
+ run("techmap -map +/ice40/brams_map.v");
}
- if (check_label(active, run_from, run_to, "fine"))
+ if (check_label("fine"))
{
- Pass::call(design, "opt -fast -mux_undef -undriven -fine");
- Pass::call(design, "memory_map");
- Pass::call(design, "opt -undriven -fine");
+ run("opt -fast -mux_undef -undriven -fine");
+ run("memory_map");
+ run("opt -undriven -fine");
if (nocarry)
- Pass::call(design, "techmap");
+ run("techmap");
else
- Pass::call(design, "techmap -map +/techmap.v -map +/ice40/arith_map.v");
- if (retime)
- Pass::call(design, "abc -dff");
- Pass::call(design, "ice40_opt");
+ run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
+ if (retime || help_mode)
+ run("abc -dff", "(only if -retime)");
+ run("ice40_opt");
}
- if (check_label(active, run_from, run_to, "map_ffs"))
+ if (check_label("map_ffs"))
{
- Pass::call(design, "dffsr2dff");
- Pass::call(design, "dff2dffe -direct-match $_DFF_*");
- Pass::call(design, "techmap -map +/ice40/cells_map.v");
- Pass::call(design, "opt_const -mux_undef");
- Pass::call(design, "simplemap");
- Pass::call(design, "ice40_ffinit");
- Pass::call(design, "ice40_ffssr");
- Pass::call(design, "ice40_opt -full");
+ run("dffsr2dff");
+ run("dff2dffe -direct-match $_DFF_*");
+ run("techmap -map +/ice40/cells_map.v");
+ run("opt_expr -mux_undef");
+ run("simplemap");
+ run("ice40_ffinit");
+ run("ice40_ffssr");
+ run("ice40_opt -full");
}
- if (check_label(active, run_from, run_to, "map_luts"))
+ if (check_label("map_luts"))
{
- if (abc2) {
- Pass::call(design, "abc");
- Pass::call(design, "ice40_opt");
+ if (abc2 || help_mode) {
+ run("abc", " (only if -abc2)");
+ run("ice40_opt", "(only if -abc2)");
}
- Pass::call(design, "abc -lut 4");
- Pass::call(design, "clean");
+ run("techmap -map +/ice40/latches_map.v");
+ run("abc -lut 4");
+ run("clean");
}
- if (check_label(active, run_from, run_to, "map_cells"))
+ if (check_label("map_cells"))
{
- Pass::call(design, "techmap -map +/ice40/cells_map.v");
- Pass::call(design, "clean");
+ run("techmap -map +/ice40/cells_map.v");
+ run("clean");
}
- if (check_label(active, run_from, run_to, "check"))
+ if (check_label("check"))
{
- Pass::call(design, "hierarchy -check");
- Pass::call(design, "stat");
- Pass::call(design, "check -noinit");
+ run("hierarchy -check");
+ run("stat");
+ run("check -noinit");
}
- if (check_label(active, run_from, run_to, "blif"))
+ if (check_label("blif"))
{
- if (!blif_file.empty())
- Pass::call(design, stringf("write_blif -gates -attr -param %s", blif_file.c_str()));
+ if (!blif_file.empty() || help_mode)
+ run(stringf("write_blif -gates -attr -param %s", help_mode ? "<file-name>" : blif_file.c_str()));
}
- if (check_label(active, run_from, run_to, "edif"))
+ if (check_label("edif"))
{
- if (!edif_file.empty())
- Pass::call(design, stringf("write_edif %s", edif_file.c_str()));
+ if (!edif_file.empty() || help_mode)
+ run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
}
-
- log_pop();
}
} SynthIce40Pass;
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-16 22:42:55 +0000