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-rw-r--r--techlibs/ice40/tests/test_bram.v19
1 files changed, 19 insertions, 0 deletions
diff --git a/techlibs/ice40/tests/test_bram.v b/techlibs/ice40/tests/test_bram.v
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+++ b/techlibs/ice40/tests/test_bram.v
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+module bram #(
+ parameter ABITS = 8, DBITS = 8
+) (
+ input clk,
+
+ input [ABITS-1:0] WR_ADDR,
+ input [DBITS-1:0] WR_DATA,
+ input WR_EN,
+
+ input [ABITS-1:0] RD_ADDR,
+ output reg [DBITS-1:0] RD_DATA
+);
+ reg [DBITS-1:0] memory [0:2**ABITS-1];
+
+ always @(posedge clk) begin
+ if (WR_EN) memory[WR_ADDR] <= WR_DATA;
+ RD_DATA <= memory[RD_ADDR];
+ end
+endmodule