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-rw-r--r--techlibs/xilinx/example_mojo_counter/example.sh6
1 files changed, 5 insertions, 1 deletions
diff --git a/techlibs/xilinx/example_mojo_counter/example.sh b/techlibs/xilinx/example_mojo_counter/example.sh
index 87af0ea3..466fadad 100644
--- a/techlibs/xilinx/example_mojo_counter/example.sh
+++ b/techlibs/xilinx/example_mojo_counter/example.sh
@@ -19,8 +19,12 @@ abc -lut 6; opt
# map internal cells to FPGA cells
techmap -map ../cells.v; opt
+# insert clock buffers
+select -set clocks */t:FDRE %x:+FDRE[C] */t:FDRE %d
+iopadmap -inpad BUFGP O:I @clocks
+
# insert i/o buffers
-iopadmap -outpad OBUF I:O -inpad BUFGP O:I
+iopadmap -outpad OBUF I:O -inpad IBUF O:I @clocks %n
# write netlist
write_edif synth.edif