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-rw-r--r--techlibs/xilinx/example_mojo_counter/README10
-rw-r--r--techlibs/xilinx/example_mojo_counter/example.sh18
-rw-r--r--techlibs/xilinx/example_mojo_counter/example.ucf14
-rw-r--r--techlibs/xilinx/example_mojo_counter/example.v14
4 files changed, 0 insertions, 56 deletions
diff --git a/techlibs/xilinx/example_mojo_counter/README b/techlibs/xilinx/example_mojo_counter/README
deleted file mode 100644
index 690a9d84..00000000
--- a/techlibs/xilinx/example_mojo_counter/README
+++ /dev/null
@@ -1,10 +0,0 @@
-
-This is a simple example for Yosys synthesis targeting the Mojo FPGA
-development board [1, 2]. Simple script for xst-based synthesis (incl.
-generation of reference edif files) and uploading to the board can be
-found here [3].
-
-[1] http://embeddedmicro.com/tutorials/mojo
-[2] https://www.sparkfun.com/products/11953
-[3] http://svn.clifford.at/handicraft/2013/mojo/
-
diff --git a/techlibs/xilinx/example_mojo_counter/example.sh b/techlibs/xilinx/example_mojo_counter/example.sh
deleted file mode 100644
index 74a0c117..00000000
--- a/techlibs/xilinx/example_mojo_counter/example.sh
+++ /dev/null
@@ -1,18 +0,0 @@
-#!/bin/bash
-
-set -ex
-
-XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE
-XILINX_PART=xc6slx9-2-tqg144
-
-../../../yosys - <<- EOT
- read_verilog example.v
- synth_xilinx -edif synth.edif
-EOT
-
-$XILINX_DIR/bin/lin64/edif2ngd -a synth.edif synth.ngo
-$XILINX_DIR/bin/lin64/ngdbuild -p $XILINX_PART -uc example.ucf synth.ngo synth.ngd
-$XILINX_DIR/bin/lin64/map -p $XILINX_PART -w -o mapped.ncd synth.ngd constraints.pcf
-$XILINX_DIR/bin/lin64/par -w mapped.ncd placed.ncd constraints.pcf
-$XILINX_DIR/bin/lin64/bitgen -w placed.ncd example.bit constraints.pcf
-
diff --git a/techlibs/xilinx/example_mojo_counter/example.ucf b/techlibs/xilinx/example_mojo_counter/example.ucf
deleted file mode 100644
index 93d97b4d..00000000
--- a/techlibs/xilinx/example_mojo_counter/example.ucf
+++ /dev/null
@@ -1,14 +0,0 @@
-NET "clk" TNM_NET = clk;
-TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%;
-
-NET "clk" LOC = P56;
-NET "ctrl" LOC = P1;
-
-NET "led_0" LOC = P134;
-NET "led_1" LOC = P133;
-NET "led_2" LOC = P132;
-NET "led_3" LOC = P131;
-NET "led_4" LOC = P127;
-NET "led_5" LOC = P126;
-NET "led_6" LOC = P124;
-NET "led_7" LOC = P123;
diff --git a/techlibs/xilinx/example_mojo_counter/example.v b/techlibs/xilinx/example_mojo_counter/example.v
deleted file mode 100644
index cb98cc1b..00000000
--- a/techlibs/xilinx/example_mojo_counter/example.v
+++ /dev/null
@@ -1,14 +0,0 @@
-module top(clk, ctrl, led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0);
-
-input clk, ctrl;
-output led_7, led_6, led_5, led_4;
-output led_3, led_2, led_1, led_0;
-
-reg [31:0] counter;
-
-always @(posedge clk)
- counter <= counter + (ctrl ? 4 : 1);
-
-assign {led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0} = counter >> 24;
-
-endmodule