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Diffstat (limited to 'techlibs/xilinx/example_zed_counter/README')
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diff --git a/techlibs/xilinx/example_zed_counter/README b/techlibs/xilinx/example_zed_counter/README new file mode 100644 index 00000000..539f24e7 --- /dev/null +++ b/techlibs/xilinx/example_zed_counter/README @@ -0,0 +1,10 @@ + +This is a simple example for Yosys synthesis targeting the ZED FPGA +development board [1, 2]. Simple script for xst-based synthesis (incl. +generation of reference edif files) and uploading to the board can be +found here [3]. + +[1] http://www.zedboard.org/ +[2] https://www.xilinx.com/zynq/ +[3] http://verilog.james.walms.co.uk/ + |