1 files changed, 36 insertions, 7 deletions

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index e7ec1e6e..590fe61d 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -34,9 +34,11 @@ bool check_label(bool &active, std::string run_from, std::string run_to, std::st
 	return active;
 }
 
-struct SynthXilinxPass : public Pass {
+struct SynthXilinxPass : public Pass
+{
 	SynthXilinxPass() : Pass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
-	virtual void help()
+
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -53,6 +55,14 @@ struct SynthXilinxPass : public Pass {
 		log("        write the design to the specified edif file. writing of an output file\n");
 		log("        is omitted if this parameter is not specified.\n");
 		log("\n");
+		log("    -blif <file>\n");
+		log("        write the design to the specified BLIF file. writing of an output file\n");
+		log("        is omitted if this parameter is not specified.\n");
+		log("\n");
+		log("    -vpr\n");
+		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
+		log("        (this feature is experimental and incomplete)\n");
+		log("\n");
 		log("    -run <from_label>:<to_label>\n");
 		log("        only run the commands between the labels (see below). an empty\n");
 		log("        from label is synonymous to 'begin', and empty to label is\n");
@@ -71,7 +81,6 @@ struct SynthXilinxPass : public Pass {
 		log("        read_verilog -lib +/xilinx/cells_sim.v\n");
 		log("        read_verilog -lib +/xilinx/cells_xtra.v\n");
 		log("        read_verilog -lib +/xilinx/brams_bb.v\n");
-		log("        read_verilog -lib +/xilinx/drams_bb.v\n");
 		log("        hierarchy -check -top <top>\n");
 		log("\n");
 		log("    flatten:     (only if -flatten)\n");
@@ -103,7 +112,7 @@ struct SynthXilinxPass : public Pass {
 		log("        clean\n");
 		log("\n");
 		log("    map_cells:\n");
-		log("        techmap -map +/xilinx/cells_map.v\n");
+		log("        techmap -map +/xilinx/cells_map.v (with -D NO_LUT in vpr mode)\n");
 		log("        dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT\n");
 		log("        clean\n");
 		log("\n");
@@ -115,14 +124,19 @@ struct SynthXilinxPass : public Pass {
 		log("    edif:     (only if -edif)\n");
 		log("        write_edif <file-name>\n");
 		log("\n");
+		log("    blif:     (only if -blif)\n");
+		log("        write_blif <file-name>\n");
+		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::string top_opt = "-auto-top";
 		std::string edif_file;
+		std::string blif_file;
 		std::string run_from, run_to;
 		bool flatten = false;
 		bool retime = false;
+		bool vpr = false;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
@@ -135,6 +149,10 @@ struct SynthXilinxPass : public Pass {
 				edif_file = args[++argidx];
 				continue;
 			}
+			if (args[argidx] == "-blif" && argidx+1 < args.size()) {
+				blif_file = args[++argidx];
+				continue;
+			}
 			if (args[argidx] == "-run" && argidx+1 < args.size()) {
 				size_t pos = args[argidx+1].find(':');
 				if (pos == std::string::npos)
@@ -151,6 +169,10 @@ struct SynthXilinxPass : public Pass {
 				retime = true;
 				continue;
 			}
+			if (args[argidx] == "-vpr") {
+				vpr = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -168,7 +190,6 @@ struct SynthXilinxPass : public Pass {
 			Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v");
 			Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v");
 			Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v");
-			Pass::call(design, "read_verilog -lib +/xilinx/drams_bb.v");
 			Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str()));
 		}
 
@@ -214,7 +235,10 @@ struct SynthXilinxPass : public Pass {
 
 		if (check_label(active, run_from, run_to, "map_cells"))
 		{
-			Pass::call(design, "techmap -map +/xilinx/cells_map.v");
+			if (vpr)
+			    Pass::call(design, "techmap -D NO_LUT -map +/xilinx/cells_map.v");
+			else
+			    Pass::call(design, "techmap -map +/xilinx/cells_map.v");
 			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT");
 			Pass::call(design, "clean");
 		}
@@ -231,6 +255,11 @@ struct SynthXilinxPass : public Pass {
 			if (!edif_file.empty())
 				Pass::call(design, stringf("write_edif %s", edif_file.c_str()));
 		}
+		if (check_label(active, run_from, run_to, "blif"))
+		{
+			if (!blif_file.empty())
+				Pass::call(design, stringf("write_blif %s", edif_file.c_str()));
+		}
 
 		log_pop();
 	}