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Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
-rw-r--r--techlibs/xilinx/synth_xilinx.cc12
1 files changed, 12 insertions, 0 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index aac8e912..0e2fdac7 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -70,6 +70,7 @@ struct SynthXilinxPass : public Pass {
log(" begin:\n");
log(" read_verilog -lib +/xilinx/cells_sim.v\n");
log(" read_verilog -lib +/xilinx/brams_bb.v\n");
+ log(" read_verilog -lib +/xilinx/drams_bb.v\n");
log(" hierarchy -check -top <top>\n");
log("\n");
log(" flatten: (only if -flatten)\n");
@@ -84,6 +85,10 @@ struct SynthXilinxPass : public Pass {
log(" memory_bram -rules +/xilinx/brams.txt\n");
log(" techmap -map +/xilinx/brams_map.v\n");
log("\n");
+ log(" dram:\n");
+ log(" memory_bram -rules +/xilinx/drams.txt\n");
+ log(" techmap -map +/xilinx/drams_map.v\n");
+ log("\n");
log(" fine:\n");
log(" opt -fast -full\n");
log(" memory_map\n");
@@ -160,6 +165,7 @@ struct SynthXilinxPass : public Pass {
{
Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v");
Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v");
+ Pass::call(design, "read_verilog -lib +/xilinx/drams_bb.v");
Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str()));
}
@@ -181,6 +187,12 @@ struct SynthXilinxPass : public Pass {
Pass::call(design, "techmap -map +/xilinx/brams_map.v");
}
+ if (check_label(active, run_from, run_to, "dram"))
+ {
+ Pass::call(design, "memory_bram -rules +/xilinx/drams.txt");
+ Pass::call(design, "techmap -map +/xilinx/drams_map.v");
+ }
+
if (check_label(active, run_from, run_to, "fine"))
{
Pass::call(design, "opt -fast -full");