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-rw-r--r--techlibs/xilinx/synth_xilinx.cc10
1 files changed, 10 insertions, 0 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 7812fa29..02207593 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -98,6 +98,10 @@ struct SynthXilinxPass : public Pass {
log(" techmap -map +/xilinx/cells_map.v\n");
log(" clean\n");
log("\n");
+ log(" check:\n");
+ log(" hierarchy -check\n");
+ log(" check -noinit\n");
+ log("\n");
log(" edif:\n");
log(" write_edif synth.edif\n");
log("\n");
@@ -195,6 +199,12 @@ struct SynthXilinxPass : public Pass {
Pass::call(design, "clean");
}
+ if (check_label(active, run_from, run_to, "check"))
+ {
+ Pass::call(design, "hierarchy -check");
+ Pass::call(design, "check -noinit");
+ }
+
if (check_label(active, run_from, run_to, "edif"))
{
if (!edif_file.empty())