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-rw-r--r--techlibs/common/Makefile.inc6
-rw-r--r--techlibs/common/simcells.v2
-rw-r--r--techlibs/common/techmap.v (renamed from techlibs/common/stdcells.v)0
3 files changed, 6 insertions, 2 deletions
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index a76d1a07..2be27b92 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -5,7 +5,7 @@ techlibs/common/blackbox.v: techlibs/common/blackbox.sed techlibs/common/simlib.
$(P) cat techlibs/common/simlib.v techlibs/common/simcells.v | $(SED) -rf techlibs/common/blackbox.sed > techlibs/common/blackbox.v.new
$(Q) mv techlibs/common/blackbox.v.new techlibs/common/blackbox.v
-EXTRA_TARGETS += share/simlib.v share/simcells.v share/blackbox.v share/pmux2mux.v
+EXTRA_TARGETS += share/simlib.v share/simcells.v share/techmap.v share/blackbox.v share/pmux2mux.v
share/simlib.v: techlibs/common/simlib.v
$(P) mkdir -p share
@@ -15,6 +15,10 @@ share/simcells.v: techlibs/common/simcells.v
$(P) mkdir -p share
$(Q) cp techlibs/common/simcells.v share/simcells.v
+share/techmap.v: techlibs/common/techmap.v
+ $(P) mkdir -p share
+ $(Q) cp techlibs/common/techmap.v share/techmap.v
+
share/blackbox.v: techlibs/common/blackbox.v
$(P) mkdir -p share
$(Q) cp techlibs/common/blackbox.v share/blackbox.v
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 5ecec789..d492c2f1 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -21,7 +21,7 @@
*
* This verilog library contains simple simulation models for the internal
* logic cells ($_INV_ , $_AND_ , ...) that are generated by the default technology
- * mapper (see "stdcells.v" in this directory) and expected by the "abc" pass.
+ * mapper (see "techmap.v" in this directory) and expected by the "abc" pass.
*
*/
diff --git a/techlibs/common/stdcells.v b/techlibs/common/techmap.v
index 54652868..54652868 100644
--- a/techlibs/common/stdcells.v
+++ b/techlibs/common/techmap.v