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-rw-r--r--techlibs/common/simlib.v11
1 files changed, 6 insertions, 5 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 76aa4a52..c2f6cb27 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -455,11 +455,12 @@ input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
- if (B_SIGNED) begin:BLOCK1
- assign Y = A[$signed(B) +: Y_WIDTH];
- end else begin:BLOCK2
- assign Y = A[B +: Y_WIDTH];
- end
+ if (Y_WIDTH > 0)
+ if (B_SIGNED) begin:BLOCK1
+ assign Y = A[$signed(B) +: Y_WIDTH];
+ end else begin:BLOCK2
+ assign Y = A[B +: Y_WIDTH];
+ end
endgenerate
endmodule