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-rw-r--r--techlibs/simlib.v1
1 files changed, 0 insertions, 1 deletions
diff --git a/techlibs/simlib.v b/techlibs/simlib.v
index 29c13503..8675a4d0 100644
--- a/techlibs/simlib.v
+++ b/techlibs/simlib.v
@@ -646,7 +646,6 @@ module \$sr (S, R, Q);
parameter WIDTH = 0;
-input CLK;
input [WIDTH-1:0] S, R;
output reg [WIDTH-1:0] Q;