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-rw-r--r--techlibs/common/simlib.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index f3d652f0..321119e3 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1036,7 +1036,7 @@ generate
end
end
end else
- if (RD_CLK_POLARITY[i] == 1) begin:rd_posclk
+ if (WR_CLK_POLARITY[i] == 1) begin:rd_posclk
always @(posedge WR_CLK[i])
if (WR_EN[i]) begin
data[ WR_ADDR[ (i+1)*ABITS-1 : i*ABITS ] - OFFSET ] <= WR_DATA[ (i+1)*WIDTH-1 : i*WIDTH ];