2 files changed, 20 insertions, 0 deletions
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 9a820f71..3b7d55c6 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -132,6 +132,12 @@ output Y;
 assign Y = ~((A | B) & (C | D));
 endmodule
 
+module \$_TBUF_ (A, E, Y);
+input A, E;
+output Y;
+assign Y = E ? A : 1'bz;
+endmodule
+
 module  \$_SR_NN_ (S, R, Q);
 input S, R;
 output reg Q;
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 275c469b..2a56b3a1 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1156,6 +1156,20 @@ endmodule
 `endif
 // --------------------------------------------------------
 
+module \$tribuf (A, EN, Y);
+
+parameter WIDTH = 0;
+
+input [WIDTH-1:0] A;
+input EN;
+output [WIDTH-1:0] Y;
+
+assign Y = EN ? A : 'bz;
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$assert (A, EN);
 
 input A, EN;