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diff --git a/tests/asicworld/code_hdl_models_half_adder_gates.v b/tests/asicworld/code_hdl_models_half_adder_gates.v
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+++ b/tests/asicworld/code_hdl_models_half_adder_gates.v
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+//-----------------------------------------------------
+// Design Name : half_adder_gates
+// File Name   : half_adder_gates.v
+// Function    : CCITT Serial CRC
+// Coder       : Deepak Kumar Tala
+//-----------------------------------------------------
+module half_adder_gates(x,y,sum,carry);
+input x,y;
+output sum,carry;
+
+and U_carry (carry,x,y);
+xor U_sum (sum,x,y);
+
+endmodule