1 files changed, 15 insertions, 0 deletions
diff --git a/tests/asicworld/code_verilog_tutorial_flip_flop.v b/tests/asicworld/code_verilog_tutorial_flip_flop.v
new file mode 100644
index 00000000..ed2e88c2
--- /dev/null
+++ b/tests/asicworld/code_verilog_tutorial_flip_flop.v
@@ -0,0 +1,15 @@
+module flif_flop (clk,reset, q, d);
+input clk, reset, d;
+output q;
+reg q;
+  	  	 
+always @ (posedge clk )
+begin
+  if (reset == 1) begin
+    q <= 0;
+  end else begin
+    q <= d;
+  end
+end
+  	  	 
+endmodule