summaryrefslogtreecommitdiff
path: root/tests/liberty
diff options
context:
space:
mode:
Diffstat (limited to 'tests/liberty')
-rw-r--r--tests/liberty/.gitignore2
-rw-r--r--tests/liberty/busdef.lib81
-rw-r--r--tests/liberty/normal.lib359
-rw-r--r--tests/liberty/processdefs.lib48
-rwxr-xr-xtests/liberty/run-test.sh10
-rw-r--r--tests/liberty/semicolextra.lib48
-rw-r--r--tests/liberty/semicolmissing.lib72
-rw-r--r--tests/liberty/small.v16
8 files changed, 636 insertions, 0 deletions
diff --git a/tests/liberty/.gitignore b/tests/liberty/.gitignore
new file mode 100644
index 00000000..e6ec49c4
--- /dev/null
+++ b/tests/liberty/.gitignore
@@ -0,0 +1,2 @@
+*.log
+test.ys
diff --git a/tests/liberty/busdef.lib b/tests/liberty/busdef.lib
new file mode 100644
index 00000000..b5e3d50b
--- /dev/null
+++ b/tests/liberty/busdef.lib
@@ -0,0 +1,81 @@
+/********************************************/
+/* */
+/* Supergate cell library for Bench marking */
+/* */
+/* Symbiotic EDA GmbH / Moseley Instruments */
+/* Niels A. Moseley */
+/* */
+/* Process: none */
+/* */
+/* Date : 02-11-2018 */
+/* Version: 1.0 */
+/* */
+/********************************************/
+
+library(supergate) {
+ technology (cmos);
+ revision : 1.0;
+
+ time_unit : "1ps";
+ pulling_resistance_unit : "1kohm";
+ voltage_unit : "1V";
+ current_unit : "1uA";
+
+ capacitive_load_unit(1,ff);
+
+ default_inout_pin_cap : 7.0;
+ default_input_pin_cap : 7.0;
+ default_output_pin_cap : 0.0;
+ default_fanout_load : 1.0;
+
+ default_wire_load_capacitance : 0.1;
+ default_wire_load_resistance : 1.0e-3;
+ default_wire_load_area : 0.0;
+
+ nom_process : 1.0;
+ nom_temperature : 25.0;
+ nom_voltage : 1.2;
+
+ delay_model : generic_cmos;
+
+ type( IO_bus_3_to_0 ) {
+ base_type : array ;
+ data_type : bit ;
+ bit_width : 4;
+ bit_from : 3 ;
+ bit_to : 0 ;
+ downto : true ;
+ }
+
+ cell (SRAM) {
+ area : 1 ;
+ memory() {
+ type : ram;
+ address_width : 4;
+ word_width : 4;
+ }
+ pin(CE1) {
+ direction : input;
+ capacitance : 0.021;
+ max_transition : 1.024;
+ switch_pin : true;
+ }
+ bus(I1) {
+ bus_type : IO_bus_3_to_0 ;
+ direction : input;
+ pin (I1[3:0]) {
+ timing() {
+ related_pin : "CE1" ;
+ timing_type : setup_rising ;
+ rise_constraint (scalar) {
+ values("0.0507786");
+ }
+ fall_constraint (scalar) {
+ values("0.0507786");
+ }
+ }
+ }
+ }
+ }
+
+} /* end */
diff --git a/tests/liberty/normal.lib b/tests/liberty/normal.lib
new file mode 100644
index 00000000..4621194d
--- /dev/null
+++ b/tests/liberty/normal.lib
@@ -0,0 +1,359 @@
+/********************************************/
+/* */
+/* Supergate cell library for Bench marking */
+/* */
+/* Symbiotic EDA GmbH / Moseley Instruments */
+/* Niels A. Moseley */
+/* */
+/* Process: none */
+/* */
+/* Date : 02-11-2018 */
+/* Version: 1.0 */
+/* */
+/********************************************/
+
+library(supergate) {
+ technology (cmos);
+ revision : 1.0;
+
+ time_unit : "1ps";
+ pulling_resistance_unit : "1kohm";
+ voltage_unit : "1V";
+ current_unit : "1uA";
+
+ capacitive_load_unit(1,ff);
+
+ default_inout_pin_cap : 7.0;
+ default_input_pin_cap : 7.0;
+ default_output_pin_cap : 0.0;
+ default_fanout_load : 1.0;
+
+ default_wire_load_capacitance : 0.1;
+ default_wire_load_resistance : 1.0e-3;
+ default_wire_load_area : 0.0;
+
+ nom_process : 1.0;
+ nom_temperature : 25.0;
+ nom_voltage : 1.2;
+
+ delay_model : generic_cmos;
+
+ /* Inverter */
+ cell (inv) {
+ area : 1;
+ pin(A) {
+ direction : input;
+ }
+
+ pin(Y) {
+ direction : output;
+ function : "A'";
+ }
+ }
+
+ /* tri-state inverter */
+ cell (tri_inv) {
+ area : 4;
+ pin(A) {
+ direction : input;
+ }
+ pin(S) {
+ direction : input;
+ }
+ pin(Z) {
+ direction : output;
+ function : "A'";
+ three_State : "S'";
+ }
+ }
+
+ cell (buffer) {
+ area : 5;
+ pin(A) {
+ direction : input;
+ }
+ pin(Y) {
+ direction : output;
+ function : "A";
+ }
+ }
+
+ /* 2-input NAND gate */
+ cell (nand2) {
+ area : 3;
+ pin(A) {
+ direction : input;
+ }
+ pin(B) {
+ direction : input;
+ }
+ pin(Y) {
+ direction: output;
+ function : "(A * B)'";
+ }
+ }
+
+ /* 2-input NOR gate */
+ cell (nor2) {
+ area : 3;
+ pin(A) {
+ direction : input;
+ }
+ pin(B) {
+ direction : input;
+ }
+ pin(Y) {
+ direction: output;
+ function : "(A + B)'";
+ }
+ }
+
+ /* 2-input XOR */
+ cell (xor2) {
+ area : 6;
+ pin(A) {
+ direction : input;
+ }
+ pin(B) {
+ direction : input;
+ }
+ pin(Y) {
+ direction: output;
+ function : "(A *B') + (A' * B)";
+ }
+ }
+
+ /* 2-input inverting MUX */
+ cell (imux2) {
+ area : 5;
+ pin(A) {
+ direction : input;
+ }
+ pin(B) {
+ direction : input;
+ }
+ pin(S) {
+ direction : input;
+ }
+ pin(Y) {
+ direction: output;
+ function : "( (A * S) + (B * S') )'";
+ }
+ }
+
+ /* D-type flip-flop with asynchronous reset and preset */
+ cell (dff) {
+ area : 6;
+ ff("IQ", "IQN") {
+ next_state : "D";
+ clocked_on : "CLK";
+ clear : "RESET";
+ preset : "PRESET";
+ clear_preset_var1 : L;
+ clear_preset_var2 : L;
+ }
+ pin(D) {
+ direction : input;
+ }
+ pin(CLK) {
+ direction : input;
+ }
+ pin(RESET) {
+ direction : input;
+ }
+ pin(PRESET) {
+ direction : input;
+ }
+ pin(Q) {
+ direction: output;
+ function : "IQ";
+ timing() {
+ timing_type : rising_edge;
+ intrinsic_rise : 65;
+ intrinsic_fall : 65;
+ rise_resistance : 0;
+ fall_resistance : 0;
+ related_pin : "CLK";
+ }
+ timing () {
+ timing_type : clear;
+ timing_sense : positive_unate;
+ intrinsic_fall : 75;
+ related_pin : "RESET";
+ }
+ timing () {
+ timing_type : preset;
+ timing_sense : negative_unate;
+ intrinsic_rise : 75;
+ related_pin : "PRESET";
+ }
+ }
+ pin(QN) {
+ direction: output;
+ function : "IQN";
+ timing() {
+ timing_type : rising_edge;
+ intrinsic_rise : 65;
+ intrinsic_fall : 65;
+ rise_resistance : 0;
+ fall_resistance : 0;
+ related_pin : "CLK";
+ }
+ timing () {
+ timing_type : preset;
+ timing_sense : negative_unate;
+ intrinsic_rise : 75;
+ related_pin : "RESET";
+ }
+ timing () {
+ timing_type : clear;
+ timing_sense : positive_unate;
+ intrinsic_fall : 75;
+ related_pin : "PRESET";
+ }
+ }
+ }
+
+ /* Latch */
+ cell(latch) {
+ area : 5;
+ latch ("IQ","IQN") {
+ enable : "G";
+ data_in : "D";
+ }
+
+ pin(D) {
+ direction : input;
+ }
+ pin(G) {
+ direction : input;
+ }
+
+ pin(Q) {
+ direction : output;
+ function : "IQ";
+ internal_node : "Q";
+
+ timing() {
+ timing_type : rising_edge;
+ intrinsic_rise : 65;
+ intrinsic_fall : 65;
+ rise_resistance : 0;
+ fall_resistance : 0;
+ related_pin : "G";
+ }
+
+ timing() {
+ timing_sense : positive_unate;
+ intrinsic_rise : 65;
+ intrinsic_fall : 65;
+ rise_resistance : 0;
+ fall_resistance : 0;
+ related_pin : "D";
+ }
+ }
+
+ pin(QN) {
+ direction : output;
+ function : "IQN";
+ internal_node : "QN";
+
+ timing() {
+ timing_type : rising_edge;
+ intrinsic_rise : 65;
+ intrinsic_fall : 65;
+ rise_resistance : 0;
+ fall_resistance : 0;
+ related_pin : "G";
+ }
+
+ timing() {
+ timing_sense : negative_unate;
+ intrinsic_rise : 65;
+ intrinsic_fall : 65;
+ rise_resistance : 0;
+ fall_resistance : 0;
+ related_pin : "D";
+ }
+ }
+ }
+
+ /* 3 input AND-OR-INVERT gate */
+ cell (aoi211) {
+ area : 3;
+ pin(A) {
+ direction : input;
+ }
+ pin(B) {
+ direction : input;
+ }
+ pin(C) {
+ direction : input;
+ }
+ pin(Y) {
+ direction: output;
+ function : "((A * B) + C)'";
+ }
+ }
+
+
+ /* 3 input OR-AND-INVERT gate */
+ cell (oai211) {
+ area : 3;
+ pin(A) {
+ direction : input;
+ }
+ pin(B) {
+ direction : input;
+ }
+ pin(C) {
+ direction : input;
+ }
+ pin(Y) {
+ direction: output;
+ function : "((A + B) * C)'";
+ }
+ }
+
+ /* half adder */
+ cell (halfadder) {
+ area : 5;
+ pin(A) {
+ direction : input;
+ }
+ pin(B) {
+ direction : input;
+ }
+ pin(C) {
+ direction : output;
+ function : "(A * B)";
+ }
+ pin(Y) {
+ direction: output;
+ function : "(A *B') + (A' * B)";
+ }
+ }
+
+ /* full adder */
+ cell (fulladder) {
+ area : 8;
+ pin(A) {
+ direction : input;
+ }
+ pin(B) {
+ direction : input;
+ }
+ pin(CI) {
+ direction : input;
+ }
+ pin(CO) {
+ direction : output;
+ function : "(((A * B)+(B * CI))+(CI * A))";
+ }
+ pin(Y) {
+ direction: output;
+ function : "((A^B)^CI)";
+ }
+ }
+
+} /* end */
diff --git a/tests/liberty/processdefs.lib b/tests/liberty/processdefs.lib
new file mode 100644
index 00000000..37a6bbaf
--- /dev/null
+++ b/tests/liberty/processdefs.lib
@@ -0,0 +1,48 @@
+/********************************************/
+/* */
+/* Supergate cell library for Bench marking */
+/* */
+/* Symbiotic EDA GmbH / Moseley Instruments */
+/* Niels A. Moseley */
+/* */
+/* Process: none */
+/* */
+/* Date : 25-03-2019 */
+/* Version: 1.0 */
+/* */
+/********************************************/
+
+library(processdefs) {
+ technology (cmos);
+ revision : 1.0;
+
+ time_unit : "1ps";
+ pulling_resistance_unit : "1kohm";
+ voltage_unit : "1V";
+ current_unit : "1uA";
+
+ capacitive_load_unit(1,ff);
+
+ default_inout_pin_cap : 7.0;
+ default_input_pin_cap : 7.0;
+ default_output_pin_cap : 0.0;
+ default_fanout_load : 1.0;
+
+ default_wire_load_capacitance : 0.1;
+ default_wire_load_resistance : 1.0e-3;
+ default_wire_load_area : 0.0;
+
+ nom_process : 1.0;
+ nom_temperature : 25.0;
+ nom_voltage : 1.2;
+
+ delay_model : generic_cmos;
+
+ define_cell_area(bond_pads,pad_slots)
+ input_voltage(cmos) {
+ vil : 0.3 * VDD ;
+ vih : 0.7 * VDD ;
+ vimin : -0.5 ;
+ vimax : VDD + 0.5 ;
+ }
+}
diff --git a/tests/liberty/run-test.sh b/tests/liberty/run-test.sh
new file mode 100755
index 00000000..7e2ed237
--- /dev/null
+++ b/tests/liberty/run-test.sh
@@ -0,0 +1,10 @@
+#!/bin/bash
+set -e
+
+for x in *.lib; do
+ echo "Running $x.."
+ echo "read_verilog small.v" > test.ys
+ echo "synth -top small" >> test.ys
+ echo "dfflibmap -liberty ${x}" >> test.ys
+ ../../yosys -ql ${x%.lib}.log -s test.ys
+done
diff --git a/tests/liberty/semicolextra.lib b/tests/liberty/semicolextra.lib
new file mode 100644
index 00000000..6a7fa77c
--- /dev/null
+++ b/tests/liberty/semicolextra.lib
@@ -0,0 +1,48 @@
+/*
+
+ Test case for https://www.reddit.com/r/yosys/comments/b5texg/yosys_fails_to_parse_apparentlycorrect_liberty/
+
+ fall_constraint (SETUP_HOLD) formatting.
+
+*/
+
+library(supergate) {
+ technology (cmos);
+ revision : 1.0;
+
+ cell (DFF) {
+ cell_footprint : dff;
+ area : 50;
+ pin(D) {
+ direction : input;
+ capacitance : 0.002;
+ timing() {
+ related_pin : "CK";
+ timing_type : setup_rising;
+
+ fall_constraint (SETUP_HOLD) { values ("0.4000, 0.3000, 0.2000, 0.1000, 0.0000", \
+ "0.4000, 0.3000, 0.2000, 0.1000, 0.000", \
+ "0.5000, 0.4000, 0.3000, 0.2000, 0.0000", \
+ "0.7000, 0.6000, 0.5000, 0.4000, 0.2000", \
+ "1.0000, 1.0000, 0.9000, 0.8000, 0.6000"); };
+ }
+ }
+
+ pin(CK) {
+ direction : input;
+ clock : true;
+ capacitance : 0.00290;
+ }
+
+ ff(IQ,IQN) {
+ clocked_on : "CK";
+ next_state : "D";
+ }
+ pin(Q) {
+ direction : output;
+ capacitance : 0.003;
+ max_capacitance : 0.3;
+ }
+ cell_leakage_power : 0.3;
+ }
+}
diff --git a/tests/liberty/semicolmissing.lib b/tests/liberty/semicolmissing.lib
new file mode 100644
index 00000000..f7c20750
--- /dev/null
+++ b/tests/liberty/semicolmissing.lib
@@ -0,0 +1,72 @@
+/********************************************/
+/* */
+/* Supergate cell library for Bench marking */
+/* */
+/* Symbiotic EDA GmbH / Moseley Instruments */
+/* Niels A. Moseley */
+/* */
+/* Process: none */
+/* */
+/* Date : 24-03-2019 */
+/* Version: 1.0 */
+/* Version: 1.1 - Removed semicolons in */
+/* full adder */
+/* */
+/********************************************/
+
+/*
+ semi colon is missing in full-adder specification
+ some TSMC liberty files are formatted this way..
+*/
+
+library(supergate) {
+ technology (cmos);
+ revision : 1.0;
+
+ time_unit : "1ps";
+ pulling_resistance_unit : "1kohm";
+ voltage_unit : "1V";
+ current_unit : "1uA";
+
+ capacitive_load_unit(1,ff);
+
+ default_inout_pin_cap : 7.0;
+ default_input_pin_cap : 7.0;
+ default_output_pin_cap : 0.0;
+ default_fanout_load : 1.0;
+
+ default_wire_load_capacitance : 0.1;
+ default_wire_load_resistance : 1.0e-3;
+ default_wire_load_area : 0.0;
+
+ nom_process : 1.0;
+ nom_temperature : 25.0;
+ nom_voltage : 1.2;
+
+ delay_model : generic_cmos;
+
+ /* full adder */
+ cell (fulladder) {
+ area : 8
+ pin(A) {
+ direction : input
+ }
+ pin(B) {
+ direction : input
+ }
+ pin(CI) {
+ direction : input
+ }
+ pin(CO) {
+ direction : output
+ function : "(((A * B)+(B * CI))+(CI * A))"
+ }
+ pin(Y) {
+ direction: output
+ function : "((A^B)^CI)"
+ }
+ }
+
+} /* end */
+
+
diff --git a/tests/liberty/small.v b/tests/liberty/small.v
new file mode 100644
index 00000000..bd94be4f
--- /dev/null
+++ b/tests/liberty/small.v
@@ -0,0 +1,16 @@
+/** small, meaningless design to test loading of liberty files */
+
+module small
+(
+ input clk,
+ output reg[7:0] count
+);
+
+initial count = 0;
+
+always @ (posedge clk)
+begin
+ count <= count + 1'b1;
+end
+
+endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-30 20:10:31 +0000