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-rw-r--r--tests/opt/opt_lut.ys4
1 files changed, 4 insertions, 0 deletions
diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys
new file mode 100644
index 00000000..59b12c35
--- /dev/null
+++ b/tests/opt/opt_lut.ys
@@ -0,0 +1,4 @@
+read_verilog opt_lut.v
+synth_ice40
+ice40_unlut
+equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3