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Diffstat (limited to 'tests/simple/dff_different_styles.v')
| -rw-r--r-- | tests/simple/dff_different_styles.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/simple/dff_different_styles.v b/tests/simple/dff_different_styles.v index 2f2737c4..7765d6e2 100644 --- a/tests/simple/dff_different_styles.v +++ b/tests/simple/dff_different_styles.v @@ -65,7 +65,7 @@ always @(posedge clk, posedge arst1, posedge arst2, negedge arst3) begin end endmodule -// SR-Flip-Flops are on the edge of well defined vewrilog constructs in terms of +// SR-Flip-Flops are on the edge of well defined Verilog constructs in terms of // simulation-implementation mismatches. The following testcases try to cover the // part that is defined and avoid the undefined cases. |