1 files changed, 1 insertions, 1 deletions
diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v
index bed5528d..40f490b7 100644
--- a/tests/simple/mem2reg.v
+++ b/tests/simple/mem2reg.v
@@ -47,7 +47,7 @@ endmodule
 
 // http://www.reddit.com/r/yosys/comments/28d9lx/problem_with_concatenation_of_two_dimensional/
 module mem2reg_test3( input clk, input [8:0] din_a, output reg [7:0] dout_a, output [7:0] dout_b);
-reg [7:0] dint_c [0:7]; 
+reg [7:0] dint_c [0:7];
 always @(posedge clk)
   begin
       {dout_a[0], dint_c[3]} <= din_a;