1 files changed, 39 insertions, 2 deletions
diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v
index 40f490b7..9839fd4a 100644
--- a/tests/simple/mem2reg.v
+++ b/tests/simple/mem2reg.v
@@ -19,9 +19,9 @@ endmodule
 
 // ------------------------------------------------------
 
-module mem2reg_test2(clk, mode, addr, data);
+module mem2reg_test2(clk, reset, mode, addr, data);
 
-input clk, mode;
+input clk, reset, mode;
 input [2:0] addr;
 output [3:0] data;
 
@@ -33,6 +33,10 @@ assign data = mem[addr];
 integer i;
 
 always @(posedge clk) begin
+	if (reset) begin
+		for (i=0; i<8; i=i+1)
+			mem[i] <= i;
+	end else
 	if (mode) begin
 		for (i=0; i<8; i=i+1)
 			mem[i] <= mem[i]+1;
@@ -55,3 +59,36 @@ always @(posedge clk)
 assign dout_b = dint_c[3];
 endmodule
 
+// ------------------------------------------------------
+
+module mem2reg_test4(result1, result2, result3);
+	output signed [9:0] result1;
+	output signed [9:0] result2;
+	output signed [9:0] result3;
+
+	wire signed [9:0] intermediate [0:3];
+
+	function integer depth2Index;
+		input integer depth;
+		depth2Index = depth;
+	endfunction
+
+	assign intermediate[depth2Index(1)] = 1;
+	assign intermediate[depth2Index(2)] = 2;
+	assign intermediate[3] = 3;
+	assign result1 = intermediate[1];
+	assign result2 = intermediate[depth2Index(2)];
+	assign result3 = intermediate[depth2Index(3)];
+endmodule
+
+// ------------------------------------------------------
+
+module mem2reg_test5(input ctrl, output out);
+	wire [0:0] foo[0:0];
+	wire [0:0] bar[0:1];
+
+	assign foo[0] = ctrl;
+	assign bar[0] = 0, bar[1] = 1;
+	assign out = bar[foo[0]];
+endmodule
+