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-rw-r--r--tests/simple/arrays02.sv16
-rw-r--r--tests/simple/attrib01_module.v21
-rw-r--r--tests/simple/attrib02_port_decl.v25
-rw-r--r--tests/simple/attrib03_parameter.v28
-rw-r--r--tests/simple/attrib04_net_var.v32
-rw-r--r--tests/simple/attrib05_port_conn.v.DISABLED21
-rw-r--r--tests/simple/attrib06_operator_suffix.v23
-rw-r--r--tests/simple/attrib07_func_call.v.DISABLED21
-rw-r--r--tests/simple/attrib08_mod_inst.v22
-rw-r--r--tests/simple/attrib09_case.v26
-rw-r--r--tests/simple/defvalue.sv22
-rw-r--r--tests/simple/dff_init.v54
-rw-r--r--tests/simple/forloops.v25
-rw-r--r--tests/simple/generate.v67
-rw-r--r--tests/simple/hierdefparam.v2
-rw-r--r--tests/simple/implicit_ports.v16
-rw-r--r--tests/simple/localparam_attr.v11
-rw-r--r--tests/simple/mem2reg.v22
-rw-r--r--tests/simple/param_attr.v11
-rw-r--r--tests/simple/peepopt.v13
-rw-r--r--tests/simple/retime.v6
-rwxr-xr-xtests/simple/run-test.sh3
-rw-r--r--tests/simple/task_func.v19
-rw-r--r--tests/simple/wandwor.v36
-rw-r--r--tests/simple/xfirrtl27
25 files changed, 568 insertions, 1 deletions
diff --git a/tests/simple/arrays02.sv b/tests/simple/arrays02.sv
new file mode 100644
index 00000000..76c2a738
--- /dev/null
+++ b/tests/simple/arrays02.sv
@@ -0,0 +1,16 @@
+module uut_arrays02(clock, we, addr, wr_data, rd_data);
+
+input clock, we;
+input [3:0] addr, wr_data;
+output [3:0] rd_data;
+reg [3:0] rd_data;
+
+reg [3:0] memory [16];
+
+always @(posedge clock) begin
+ if (we)
+ memory[addr] <= wr_data;
+ rd_data <= memory[addr];
+end
+
+endmodule
diff --git a/tests/simple/attrib01_module.v b/tests/simple/attrib01_module.v
new file mode 100644
index 00000000..adef34f5
--- /dev/null
+++ b/tests/simple/attrib01_module.v
@@ -0,0 +1,21 @@
+module bar(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output reg out;
+
+ always @(posedge clk)
+ if (rst) out <= 1'd0;
+ else out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output wire out;
+
+ bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib02_port_decl.v b/tests/simple/attrib02_port_decl.v
new file mode 100644
index 00000000..3505e726
--- /dev/null
+++ b/tests/simple/attrib02_port_decl.v
@@ -0,0 +1,25 @@
+module bar(clk, rst, inp, out);
+ (* this_is_clock = 1 *)
+ input wire clk;
+ (* this_is_reset = 1 *)
+ input wire rst;
+ input wire inp;
+ (* an_output_register = 1*)
+ output reg out;
+
+ always @(posedge clk)
+ if (rst) out <= 1'd0;
+ else out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ (* this_is_the_master_clock *)
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output wire out;
+
+ bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib03_parameter.v b/tests/simple/attrib03_parameter.v
new file mode 100644
index 00000000..562d225c
--- /dev/null
+++ b/tests/simple/attrib03_parameter.v
@@ -0,0 +1,28 @@
+module bar(clk, rst, inp, out);
+
+ (* bus_width *)
+ parameter WIDTH = 2;
+
+ (* an_attribute_on_localparam = 55 *)
+ localparam INCREMENT = 5;
+
+ input wire clk;
+ input wire rst;
+ input wire [WIDTH-1:0] inp;
+ output reg [WIDTH-1:0] out;
+
+ always @(posedge clk)
+ if (rst) out <= 0;
+ else out <= inp + INCREMENT;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire [7:0] inp;
+ output wire [7:0] out;
+
+ bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib04_net_var.v b/tests/simple/attrib04_net_var.v
new file mode 100644
index 00000000..8b552340
--- /dev/null
+++ b/tests/simple/attrib04_net_var.v
@@ -0,0 +1,32 @@
+module bar(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output reg out;
+
+ (* this_is_a_prescaler *)
+ reg [7:0] counter;
+
+ (* temp_wire *)
+ wire out_val;
+
+ always @(posedge clk)
+ counter <= counter + 1;
+
+ assign out_val = inp ^ counter[4];
+
+ always @(posedge clk)
+ if (rst) out <= 1'd0;
+ else out <= out_val;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output wire out;
+
+ bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib05_port_conn.v.DISABLED b/tests/simple/attrib05_port_conn.v.DISABLED
new file mode 100644
index 00000000..e20e6631
--- /dev/null
+++ b/tests/simple/attrib05_port_conn.v.DISABLED
@@ -0,0 +1,21 @@
+module bar(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output reg out;
+
+ always @(posedge clk)
+ if (rst) out <= 1'd0;
+ else out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output wire out;
+
+ bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
+endmodule
+
diff --git a/tests/simple/attrib06_operator_suffix.v b/tests/simple/attrib06_operator_suffix.v
new file mode 100644
index 00000000..e21173c5
--- /dev/null
+++ b/tests/simple/attrib06_operator_suffix.v
@@ -0,0 +1,23 @@
+module bar(clk, rst, inp_a, inp_b, out);
+ input wire clk;
+ input wire rst;
+ input wire [7:0] inp_a;
+ input wire [7:0] inp_b;
+ output reg [7:0] out;
+
+ always @(posedge clk)
+ if (rst) out <= 0;
+ else out <= inp_a + (* ripple_adder *) inp_b;
+
+endmodule
+
+module foo(clk, rst, inp_a, inp_b, out);
+ input wire clk;
+ input wire rst;
+ input wire [7:0] inp_a;
+ input wire [7:0] inp_b;
+ output wire [7:0] out;
+
+ bar bar_instance (clk, rst, inp_a, inp_b, out);
+endmodule
+
diff --git a/tests/simple/attrib07_func_call.v.DISABLED b/tests/simple/attrib07_func_call.v.DISABLED
new file mode 100644
index 00000000..f55ef231
--- /dev/null
+++ b/tests/simple/attrib07_func_call.v.DISABLED
@@ -0,0 +1,21 @@
+function [7:0] do_add;
+ input [7:0] inp_a;
+ input [7:0] inp_b;
+
+ do_add = inp_a + inp_b;
+
+endfunction
+
+module foo(clk, rst, inp_a, inp_b, out);
+ input wire clk;
+ input wire rst;
+ input wire [7:0] inp_a;
+ input wire [7:0] inp_b;
+ output wire [7:0] out;
+
+ always @(posedge clk)
+ if (rst) out <= 0;
+ else out <= do_add (* combinational_adder *) (inp_a, inp_b);
+
+endmodule
+
diff --git a/tests/simple/attrib08_mod_inst.v b/tests/simple/attrib08_mod_inst.v
new file mode 100644
index 00000000..c5a32234
--- /dev/null
+++ b/tests/simple/attrib08_mod_inst.v
@@ -0,0 +1,22 @@
+module bar(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output reg out;
+
+ always @(posedge clk)
+ if (rst) out <= 1'd0;
+ else out <= ~inp;
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire inp;
+ output wire out;
+
+ (* my_module_instance = 99 *)
+ bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/attrib09_case.v b/tests/simple/attrib09_case.v
new file mode 100644
index 00000000..8551bf9d
--- /dev/null
+++ b/tests/simple/attrib09_case.v
@@ -0,0 +1,26 @@
+module bar(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire [1:0] inp;
+ output reg [1:0] out;
+
+ always @(inp)
+ (* full_case, parallel_case *)
+ case(inp)
+ 2'd0: out <= 2'd3;
+ 2'd1: out <= 2'd2;
+ 2'd2: out <= 2'd1;
+ 2'd3: out <= 2'd0;
+ endcase
+
+endmodule
+
+module foo(clk, rst, inp, out);
+ input wire clk;
+ input wire rst;
+ input wire [1:0] inp;
+ output wire [1:0] out;
+
+ bar bar_instance (clk, rst, inp, out);
+endmodule
+
diff --git a/tests/simple/defvalue.sv b/tests/simple/defvalue.sv
new file mode 100644
index 00000000..b0a087ec
--- /dev/null
+++ b/tests/simple/defvalue.sv
@@ -0,0 +1,22 @@
+module top(input clock, input [3:0] delta, output [3:0] cnt1, cnt2);
+ cnt #(1) foo (.clock, .cnt(cnt1), .delta);
+ cnt #(2) bar (.clock, .cnt(cnt2));
+endmodule
+
+module cnt #(
+ parameter integer initval = 0
+) (
+ input clock,
+ output logic [3:0] cnt = initval,
+`ifdef __ICARUS__
+ input [3:0] delta
+`else
+ input [3:0] delta = 10
+`endif
+);
+`ifdef __ICARUS__
+ assign (weak0, weak1) delta = 10;
+`endif
+ always @(posedge clock)
+ cnt <= cnt + delta;
+endmodule
diff --git a/tests/simple/dff_init.v b/tests/simple/dff_init.v
new file mode 100644
index 00000000..375ea5c4
--- /dev/null
+++ b/tests/simple/dff_init.v
@@ -0,0 +1,54 @@
+module dff0_test(n1, n1_inv, clk);
+ input clk;
+ output n1;
+ reg n1 = 32'd0;
+ output n1_inv;
+ always @(posedge clk)
+ n1 <= n1_inv;
+ assign n1_inv = ~n1;
+endmodule
+
+module dff1_test(n1, n1_inv, clk);
+ input clk;
+ (* init = 32'd1 *)
+ output n1;
+ reg n1 = 32'd1;
+ output n1_inv;
+ always @(posedge clk)
+ n1 <= n1_inv;
+ assign n1_inv = ~n1;
+endmodule
+
+module dff0a_test(n1, n1_inv, clk);
+ input clk;
+ (* init = 32'd0 *) // Must be consistent with reg initialiser below
+ output n1;
+ reg n1 = 32'd0;
+ output n1_inv;
+ always @(posedge clk)
+ n1 <= n1_inv;
+ assign n1_inv = ~n1;
+endmodule
+
+module dff1a_test(n1, n1_inv, clk);
+ input clk;
+ (* init = 32'd1 *) // Must be consistent with reg initialiser below
+ output n1;
+ reg n1 = 32'd1;
+ output n1_inv;
+ always @(posedge clk)
+ n1 <= n1_inv;
+ assign n1_inv = ~n1;
+endmodule
+
+module dff_test_997 (y, clk, wire4);
+// https://github.com/YosysHQ/yosys/issues/997
+ output wire [1:0] y;
+ input clk;
+ input signed wire4;
+ reg [1:0] reg10 = 0;
+ always @(posedge clk) begin
+ reg10 <= wire4;
+ end
+ assign y = reg10;
+endmodule
diff --git a/tests/simple/forloops.v b/tests/simple/forloops.v
new file mode 100644
index 00000000..8665222d
--- /dev/null
+++ b/tests/simple/forloops.v
@@ -0,0 +1,25 @@
+module forloops01 (input clk, a, b, output reg [3:0] p, q, x, y);
+ integer k;
+ always @(posedge clk) begin
+ for (k=0; k<2; k=k+1)
+ p[2*k +: 2] = {a, b} ^ {2{k}};
+ x <= k + {a, b};
+ end
+ always @* begin
+ for (k=0; k<4; k=k+1)
+ q[k] = {~a, ~b, a, b} >> k[1:0];
+ y = k - {a, b};
+ end
+endmodule
+
+module forloops02 (input clk, a, b, output reg [3:0] q, x, output [3:0] y);
+ integer k;
+ always @* begin
+ for (k=0; k<4; k=k+1)
+ q[k] = {~a, ~b, a, b} >> k[1:0];
+ end
+ always @* begin
+ x = k + {a, b};
+ end
+ assign y = k - {a, b};
+endmodule
diff --git a/tests/simple/generate.v b/tests/simple/generate.v
index 24eb4462..0e353ad9 100644
--- a/tests/simple/generate.v
+++ b/tests/simple/generate.v
@@ -90,5 +90,72 @@ generate
endcase
end
endgenerate
+endmodule
+
+// ------------------------------------------
+
+module gen_test4(a, b);
+
+input [3:0] a;
+output [3:0] b;
+
+genvar i;
+generate
+ for (i=0; i < 3; i=i+1) begin : foo
+ localparam PREV = i - 1;
+ wire temp;
+ if (i == 0)
+ assign temp = a[0];
+ else
+ assign temp = foo[PREV].temp & a[i];
+ assign b[i] = temp;
+ end
+endgenerate
+endmodule
+
+// ------------------------------------------
+
+module gen_test5(input_bits, out);
+
+parameter WIDTH = 256;
+parameter CHUNK = 4;
+
+input [WIDTH-1:0] input_bits;
+output out;
+
+genvar step, i, j;
+generate
+ for (step = 1; step <= WIDTH; step = step * CHUNK) begin : steps
+ localparam PREV = step / CHUNK;
+ localparam DIM = WIDTH / step;
+ for (i = 0; i < DIM; i = i + 1) begin : outer
+ localparam LAST_START = i * CHUNK;
+ for (j = 0; j < CHUNK; j = j + 1) begin : inner
+ wire temp;
+ if (step == 1)
+ assign temp = input_bits[i];
+ else if (j == 0)
+ assign temp = steps[PREV].outer[LAST_START].val;
+ else
+ assign temp
+ = steps[step].outer[i].inner[j-1].temp
+ & steps[PREV].outer[LAST_START + j].val;
+ end
+ wire val;
+ assign val = steps[step].outer[i].inner[CHUNK - 1].temp;
+ end
+ end
+endgenerate
+assign out = steps[WIDTH].outer[0].val;
+endmodule
+// ------------------------------------------
+
+module gen_test6(output [3:0] o);
+generate
+ genvar i;
+ for (i = 3; i >= 0; i = i-1) begin
+ assign o[i] = 1'b0;
+ end
+endgenerate
endmodule
diff --git a/tests/simple/hierdefparam.v b/tests/simple/hierdefparam.v
index ff92c38b..c9368ca7 100644
--- a/tests/simple/hierdefparam.v
+++ b/tests/simple/hierdefparam.v
@@ -1,3 +1,5 @@
+`default_nettype none
+
module hierdefparam_top(input [7:0] A, output [7:0] Y);
generate begin:foo
hierdefparam_a mod_a(.A(A), .Y(Y));
diff --git a/tests/simple/implicit_ports.v b/tests/simple/implicit_ports.v
new file mode 100644
index 00000000..8b0a6f38
--- /dev/null
+++ b/tests/simple/implicit_ports.v
@@ -0,0 +1,16 @@
+// Test implicit port connections
+module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result);
+ assign cout = cin;
+ assign result = a + b;
+endmodule
+
+module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout);
+ wire cin = 1;
+ alu alu (
+ .a(a),
+ .b, // Implicit connection is equivalent to .b(b)
+ .cin(), // Explicitely unconnected
+ .cout(cout),
+ .result(alu_result)
+ );
+endmodule
diff --git a/tests/simple/localparam_attr.v b/tests/simple/localparam_attr.v
new file mode 100644
index 00000000..2ef76c71
--- /dev/null
+++ b/tests/simple/localparam_attr.v
@@ -0,0 +1,11 @@
+module uut_localparam_attr (I, O);
+
+(* LOCALPARAM_ATTRIBUTE = "attribute_content" *)
+localparam WIDTH = 1;
+
+input wire [WIDTH-1:0] I;
+output wire [WIDTH-1:0] O;
+
+assign O = I;
+
+endmodule
diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v
index 9839fd4a..10042678 100644
--- a/tests/simple/mem2reg.v
+++ b/tests/simple/mem2reg.v
@@ -92,3 +92,25 @@ module mem2reg_test5(input ctrl, output out);
assign out = bar[foo[0]];
endmodule
+// ------------------------------------------------------
+
+module mem2reg_test6 (din, dout);
+ input wire [3:0] din;
+ output reg [3:0] dout;
+
+ reg [1:0] din_array [1:0];
+ reg [1:0] dout_array [1:0];
+
+ always @* begin
+ din_array[0] = din[0 +: 2];
+ din_array[1] = din[2 +: 2];
+
+ dout_array[0] = din_array[0];
+ dout_array[1] = din_array[1];
+
+ {dout_array[0][1], dout_array[0][0]} = dout_array[0][0] + dout_array[1][0];
+
+ dout[0 +: 2] = dout_array[0];
+ dout[2 +: 2] = dout_array[1];
+ end
+endmodule
diff --git a/tests/simple/param_attr.v b/tests/simple/param_attr.v
new file mode 100644
index 00000000..34d63a34
--- /dev/null
+++ b/tests/simple/param_attr.v
@@ -0,0 +1,11 @@
+module uut_param_attr (I, O);
+
+(* PARAMETER_ATTRIBUTE = "attribute_content" *)
+parameter WIDTH = 1;
+
+input wire [WIDTH-1:0] I;
+output wire [WIDTH-1:0] O;
+
+assign O = I;
+
+endmodule
diff --git a/tests/simple/peepopt.v b/tests/simple/peepopt.v
new file mode 100644
index 00000000..1bf42789
--- /dev/null
+++ b/tests/simple/peepopt.v
@@ -0,0 +1,13 @@
+module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
+assign o = i[s*W+:W];
+endmodule
+
+module peepopt_shiftmul_1 (output y, input [2:0] w);
+assign y = 1'b1 >> (w * (3'b110));
+endmodule
+
+module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
+wire [3:0] t;
+assign t = i * 3;
+assign o = t / 3;
+endmodule
diff --git a/tests/simple/retime.v b/tests/simple/retime.v
new file mode 100644
index 00000000..30b6087d
--- /dev/null
+++ b/tests/simple/retime.v
@@ -0,0 +1,6 @@
+module retime_test(input clk, input [7:0] a, output z);
+ reg [7:0] ff = 8'hF5;
+ always @(posedge clk)
+ ff <= {ff[6:0], ^a};
+ assign z = ff[7];
+endmodule
diff --git a/tests/simple/run-test.sh b/tests/simple/run-test.sh
index aaa1cf94..967ac49f 100755
--- a/tests/simple/run-test.sh
+++ b/tests/simple/run-test.sh
@@ -17,4 +17,5 @@ if ! which iverilog > /dev/null ; then
exit 1
fi
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v
+shopt -s nullglob
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.{sv,v}
diff --git a/tests/simple/task_func.v b/tests/simple/task_func.v
index fa50c1d5..f6e902f6 100644
--- a/tests/simple/task_func.v
+++ b/tests/simple/task_func.v
@@ -120,3 +120,22 @@ module task_func_test04(input [7:0] in, output [7:0] out1, out2, out3, out4);
assign out3 = test3(in);
assign out4 = test4(in);
endmodule
+
+// -------------------------------------------------------------------
+
+// https://github.com/YosysHQ/yosys/issues/857
+module task_func_test05(data_in,data_out,clk);
+ output reg data_out;
+ input data_in;
+ input clk;
+
+ task myTask;
+ output out;
+ input in;
+ out = in;
+ endtask
+
+ always @(posedge clk) begin
+ myTask(data_out,data_in);
+ end
+endmodule
diff --git a/tests/simple/wandwor.v b/tests/simple/wandwor.v
new file mode 100644
index 00000000..34404aa2
--- /dev/null
+++ b/tests/simple/wandwor.v
@@ -0,0 +1,36 @@
+module wandwor_test0 (A, B, C, D, X, Y, Z);
+ input A, B, C, D;
+ output wor X;
+ output wand Y;
+ output Z;
+
+ assign X = A, X = B, Y = C, Y = D;
+ foo foo_0 (C, D, X);
+ foo foo_1 (A, B, Y);
+ foo foo_2 (X, Y, Z);
+endmodule
+
+module wandwor_test1 (A, B, C, D, X, Y, Z);
+ input [3:0] A, B, C, D;
+ output wor [3:0] X;
+ output wand [3:0] Y;
+ output Z;
+
+ bar bar_inst (
+ .I0({A, B}),
+ .I1({B, A}),
+ .O({X, Y})
+ );
+
+ assign X = C, X = D;
+ assign Y = C, Y = D;
+ assign Z = ^{X,Y};
+endmodule
+
+module foo(input I0, I1, output O);
+ assign O = I0 ^ I1;
+endmodule
+
+module bar(input [7:0] I0, I1, output [7:0] O);
+ assign O = I0 + I1;
+endmodule
diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl
new file mode 100644
index 00000000..ba61a447
--- /dev/null
+++ b/tests/simple/xfirrtl
@@ -0,0 +1,27 @@
+# This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures.
+arraycells.v inst id[0] of
+dff_different_styles.v
+dff_init.v Initial value not supported
+generate.v combinational loop
+hierdefparam.v inst id[0] of
+i2c_master_tests.v $adff
+macros.v drops modules
+mem2reg.v drops modules
+mem_arst.v $adff
+memory.v $adff
+multiplier.v inst id[0] of
+muxtree.v drops modules
+omsp_dbg_uart.v $adff
+operators.v $pow
+partsel.v drops modules
+process.v drops modules
+realexpr.v drops modules
+retime.v Initial value (11110101) for (retime_test.ff) not supported
+scopes.v original verilog issues ( -x where x isn't declared signed)
+sincos.v $adff
+specify.v no code (empty module generates error
+subbytes.v $adff
+task_func.v drops modules
+values.v combinational loop
+vloghammer.v combinational loop
+wreduce.v original verilog issues ( -x where x isn't declared signed)