diff options
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/asicworld/code_hdl_models_arbiter_tb.v | 28 | ||||
| -rw-r--r-- | tests/asicworld/code_verilog_tutorial_counter_tb.v | 36 | ||||
| -rw-r--r-- | tests/asicworld/code_verilog_tutorial_first_counter_tb.v | 15 | ||||
| -rw-r--r-- | tests/asicworld/code_verilog_tutorial_fsm_full_tb.v | 12 | ||||
| -rw-r--r-- | tests/simple/constmuldivmod.v | 27 | ||||
| -rw-r--r-- | tests/simple/mem2reg.v | 41 | ||||
| -rw-r--r-- | tests/simple/memory.v | 64 | ||||
| -rwxr-xr-x | tests/tools/autotest.sh | 59 | ||||
| -rw-r--r-- | tests/tools/cmp_tbdata.c | 4 |
9 files changed, 203 insertions, 83 deletions
diff --git a/tests/asicworld/code_hdl_models_arbiter_tb.v b/tests/asicworld/code_hdl_models_arbiter_tb.v index 5e7bf46b..78d1168e 100644 --- a/tests/asicworld/code_hdl_models_arbiter_tb.v +++ b/tests/asicworld/code_hdl_models_arbiter_tb.v @@ -1,11 +1,11 @@ module testbench (); -reg clk; -reg rst; -reg req3; -reg req2; -reg req1; -reg req0; +reg clk = 0; +reg rst = 1; +reg req3 = 0; +reg req2 = 0; +reg req1 = 0; +reg req0 = 0; wire gnt3; wire gnt2; wire gnt1; @@ -13,17 +13,15 @@ wire gnt0; // Clock generator always #1 clk = ~clk; +integer file; + +always @(posedge clk) + $fdisplay(file, "%b", {gnt3, gnt2, gnt1, gnt0}); initial begin - $dumpfile ("arbiter.vcd"); - $dumpvars(); - clk = 0; - rst = 1; - req0 = 0; - req1 = 0; - req2 = 0; - req3 = 0; - #10 rst = 0; + file = $fopen(`outfile); + repeat (5) @ (posedge clk); + rst <= 0; repeat (1) @ (posedge clk); req0 <= 1; repeat (1) @ (posedge clk); diff --git a/tests/asicworld/code_verilog_tutorial_counter_tb.v b/tests/asicworld/code_verilog_tutorial_counter_tb.v index 50481454..33d54050 100644 --- a/tests/asicworld/code_verilog_tutorial_counter_tb.v +++ b/tests/asicworld/code_verilog_tutorial_counter_tb.v @@ -15,9 +15,10 @@ /////////////////////////////////////////////////////////////////////////// module testbench; -reg clk, reset, enable; +integer file; +reg clk = 0, reset = 0, enable = 0; wire [3:0] count; -reg dut_error; +reg dut_error = 0; counter U0 ( .clk (clk), @@ -30,34 +31,21 @@ event reset_enable; event terminate_sim; initial -begin - $display ("###################################################"); - clk = 0; - reset = 0; - enable = 0; - dut_error = 0; -end + file = $fopen(`outfile); always #5 clk = !clk; initial -begin - $dumpfile ("counter.vcd"); - $dumpvars; -end - - -initial @ (terminate_sim) begin - $display ("Terminating simulation"); + $fdisplay (file, "Terminating simulation"); if (dut_error == 0) begin - $display ("Simulation Result : PASSED"); + $fdisplay (file, "Simulation Result : PASSED"); end else begin - $display ("Simulation Result : FAILED"); + $fdisplay (file, "Simulation Result : FAILED"); end - $display ("###################################################"); + $fdisplay (file, "###################################################"); #1 $finish; end @@ -69,11 +57,11 @@ initial forever begin @ (reset_enable); @ (negedge clk) - $display ("Applying reset"); + $fdisplay (file, "Applying reset"); reset = 1; @ (negedge clk) reset = 0; - $display ("Came out of Reset"); + $fdisplay (file, "Came out of Reset"); -> reset_done; end @@ -103,8 +91,8 @@ else if ( enable == 1'b1) always @ (negedge clk) if (count_compare != count) begin - $display ("DUT ERROR AT TIME%d",$time); - $display ("Expected value %d, Got Value %d", count_compare, count); + $fdisplay (file, "DUT ERROR AT TIME%d",$time); + $fdisplay (file, "Expected value %d, Got Value %d", count_compare, count); dut_error = 1; #5 -> terminate_sim; end diff --git a/tests/asicworld/code_verilog_tutorial_first_counter_tb.v b/tests/asicworld/code_verilog_tutorial_first_counter_tb.v index f065732b..806e1773 100644 --- a/tests/asicworld/code_verilog_tutorial_first_counter_tb.v +++ b/tests/asicworld/code_verilog_tutorial_first_counter_tb.v @@ -1,16 +1,13 @@ module testbench(); // Declare inputs as regs and outputs as wires -reg clock, reset, enable; +reg clock = 1, reset = 0, enable = 0; wire [3:0] counter_out; +integer file; // Initialize all variables initial begin - $display ("time\t clk reset enable counter"); - $monitor ("%g\t %b %b %b %b", - $time, clock, reset, enable, counter_out); - clock = 1; // initial value of clock - reset = 0; // initial value of reset - enable = 0; // initial value of enable + file = $fopen(`outfile); + $fdisplay (file, "time\t clk reset enable counter"); #5 reset = 1; // Assert the reset #10 reset = 0; // De-assert the reset #10 enable = 1; // Assert enable @@ -18,6 +15,10 @@ initial begin #5 $finish; // Terminate simulation end +always @(negedge clock) + $fdisplay (file, "%g\t %b %b %b %b", + $time, clock, reset, enable, counter_out); + // Clock generator initial begin #1; diff --git a/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v b/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v index 2e944895..a8e15568 100644 --- a/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v +++ b/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v @@ -1,14 +1,14 @@ module testbench(); -reg clock , reset ; +reg clock = 0 , reset ; reg req_0 , req_1 , req_2 , req_3; wire gnt_0 , gnt_1 , gnt_2 , gnt_3 ; +integer file; initial begin // $dumpfile("testbench.vcd"); // $dumpvars(0, testbench); - $display("Time\t R0 R1 R2 R3 G0 G1 G2 G3"); - $monitor("%g\t %b %b %b %b %b %b %b %b", - $time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3); + file = $fopen(`outfile); + $fdisplay(file, "Time\t R0 R1 R2 R3 G0 G1 G2 G3"); clock = 0; reset = 1; req_0 = 0; @@ -28,6 +28,10 @@ initial begin #10 $finish; end +always @(negedge clock) + $fdisplay(file, "%g\t %b %b %b %b %b %b %b %b", + $time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3); + initial begin #1; forever diff --git a/tests/simple/constmuldivmod.v b/tests/simple/constmuldivmod.v new file mode 100644 index 00000000..d1d8be86 --- /dev/null +++ b/tests/simple/constmuldivmod.v @@ -0,0 +1,27 @@ +module constmuldivmod(input [7:0] A, input [2:0] mode, output reg [7:0] Y); + always @* begin + case (mode) + 0: Y = A / 8'd0; + 1: Y = A % 8'd0; + 2: Y = A * 8'd0; + + 3: Y = A / 8'd1; + 4: Y = A % 8'd1; + 5: Y = A * 8'd1; + + 6: Y = A / 8'd2; + 7: Y = A % 8'd2; + 8: Y = A * 8'd2; + + 9: Y = A / 8'd4; + 10: Y = A % 8'd4; + 11: Y = A * 8'd4; + + 12: Y = A / 8'd8; + 13: Y = A % 8'd8; + 14: Y = A * 8'd8; + + default: Y = 8'd16 * A; + endcase + end +endmodule diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v index 40f490b7..9839fd4a 100644 --- a/tests/simple/mem2reg.v +++ b/tests/simple/mem2reg.v @@ -19,9 +19,9 @@ endmodule // ------------------------------------------------------ -module mem2reg_test2(clk, mode, addr, data); +module mem2reg_test2(clk, reset, mode, addr, data); -input clk, mode; +input clk, reset, mode; input [2:0] addr; output [3:0] data; @@ -33,6 +33,10 @@ assign data = mem[addr]; integer i; always @(posedge clk) begin + if (reset) begin + for (i=0; i<8; i=i+1) + mem[i] <= i; + end else if (mode) begin for (i=0; i<8; i=i+1) mem[i] <= mem[i]+1; @@ -55,3 +59,36 @@ always @(posedge clk) assign dout_b = dint_c[3]; endmodule +// ------------------------------------------------------ + +module mem2reg_test4(result1, result2, result3); + output signed [9:0] result1; + output signed [9:0] result2; + output signed [9:0] result3; + + wire signed [9:0] intermediate [0:3]; + + function integer depth2Index; + input integer depth; + depth2Index = depth; + endfunction + + assign intermediate[depth2Index(1)] = 1; + assign intermediate[depth2Index(2)] = 2; + assign intermediate[3] = 3; + assign result1 = intermediate[1]; + assign result2 = intermediate[depth2Index(2)]; + assign result3 = intermediate[depth2Index(3)]; +endmodule + +// ------------------------------------------------------ + +module mem2reg_test5(input ctrl, output out); + wire [0:0] foo[0:0]; + wire [0:0] bar[0:1]; + + assign foo[0] = ctrl; + assign bar[0] = 0, bar[1] = 1; + assign out = bar[foo[0]]; +endmodule + diff --git a/tests/simple/memory.v b/tests/simple/memory.v index d58ed9d1..f38bdafd 100644 --- a/tests/simple/memory.v +++ b/tests/simple/memory.v @@ -243,3 +243,67 @@ module memtest10(input clk, input [5:0] din, output [5:0] dout); assign dout = queue[3]; endmodule + +// ---------------------------------------------------------- + +module memtest11(clk, wen, waddr, raddr, wdata, rdata); + input clk, wen; + input [1:0] waddr, raddr; + input [7:0] wdata; + output [7:0] rdata; + + reg [7:0] mem [3:0]; + + assign rdata = mem[raddr]; + + always @(posedge clk) begin + if (wen) + mem[waddr] <= wdata; + else + mem[waddr] <= mem[waddr]; + end +endmodule + +// ---------------------------------------------------------- + +module memtest12 ( + input clk, + input [1:0] adr, + input [1:0] din, + output reg [1:0] q +); + reg [1:0] ram [3:0]; + always@(posedge clk) + {ram[adr], q} <= {din, ram[adr]}; +endmodule + +// ---------------------------------------------------------- + +module memtest13 ( + input clk, rst, + input [1:0] a1, a2, a3, a4, a5, a6, + input [3:0] off1, off2, + input [31:5] din1, + input [3:0] din2, din3, + output reg [3:0] dout1, dout2, + output reg [31:5] dout3 +); + reg [31:5] mem [0:3]; + + always @(posedge clk) begin + if (rst) begin + mem[0] <= 0; + mem[1] <= 0; + mem[2] <= 0; + mem[3] <= 0; + end else begin + mem[a1] <= din1; + mem[a2][14:11] <= din2; + mem[a3][5 + off1 +: 4] <= din3; + dout1 <= mem[a4][12:9]; + dout2 <= mem[a5][5 + off2 +: 4]; + dout3 <= mem[a6]; + end + end +endmodule + diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 76668bed..d0b0a89d 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -10,16 +10,19 @@ makejmode=false frontend="verilog" backend_opts="-noattr -noexpr" autotb_opts="" +include_opts="" +xinclude_opts="" +minclude_opts="" scriptfiles="" scriptopt="" toolsdir="$(cd $(dirname $0); pwd)" warn_iverilog_git=false if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then - ( set -ex; gcc -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1 + ( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1 fi -while getopts xmGl:wkjvref:s:p:n: opt; do +while getopts xmGl:wkjvref:s:p:n:S:I: opt; do case "$opt" in x) use_xsim=true ;; @@ -50,34 +53,32 @@ while getopts xmGl:wkjvref:s:p:n: opt; do scriptopt="$OPTARG" ;; n) autotb_opts="$autotb_opts -n $OPTARG" ;; + S) + autotb_opts="$autotb_opts -seed $OPTARG" ;; + I) + include_opts="$include_opts -I $OPTARG" + xinclude_opts="$xinclude_opts -i $OPTARG" + minclude_opts="$minclude_opts +incdir+$OPTARG" ;; *) - echo "Usage: $0 [-x|-m] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] verilog-files\n" >&2 + echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] verilog-files\n" >&2 exit 1 esac done -create_ref() { - cp "$1" "$2.v" -} - compile_and_run() { exe="$1"; output="$2"; shift 2 if $use_modelsim; then altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; ) /opt/altera/$altver/modelsim_ase/bin/vlib work - /opt/altera/$altver/modelsim_ase/bin/vlog "$@" - /opt/altera/$altver/modelsim_ase/bin/vsim -c -do 'run -all; exit;' testbench | grep '#OUT#' > "$output" + /opt/altera/$altver/modelsim_ase/bin/vlog $minclude_opts +define+outfile=\"$output\" "$@" + /opt/altera/$altver/modelsim_ase/bin/vsim -c -do 'run -all; exit;' testbench elif $use_xsim; then - ( - set +x - files=( "$@" ) - xilver=$( ls -v /opt/Xilinx/Vivado/ | grep '^[0-9]' | tail -n1; ) - /opt/Xilinx/Vivado/$xilver/bin/xvlog "${files[@]}" - /opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench | grep '#OUT#' > "$output" - ) + xilver=$( ls -v /opt/Xilinx/Vivado/ | grep '^[0-9]' | tail -n1; ) + /opt/Xilinx/Vivado/$xilver/bin/xvlog $xinclude_opts -d outfile=\"$output\" "$@" + /opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench else - iverilog -s testbench -o "$exe" "$@" - vvp -n "$exe" > "$output" + iverilog $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@" + vvp -n "$exe" fi } @@ -108,15 +109,15 @@ do fn=$(basename $fn) bn=$(basename $bn) - cp ../$fn $fn + egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.v + if [ ! -f ../${bn}_tb.v ]; then - "$toolsdir"/../../yosys -b "test_autotb $autotb_opts" -o ${bn}_tb.v $fn + "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v else cp ../${bn}_tb.v ${bn}_tb.v fi if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi - create_ref $fn ${bn}_ref - compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs + compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi test_count=0 @@ -131,22 +132,22 @@ do test_count=$(( test_count + 1 )) } - if [ "$frontend" = "verific" -o "$frontend" = "verific_gates" ] && grep -q VERIFIC-SKIP $fn; then + if [ "$frontend" = "verific" -o "$frontend" = "verific_gates" ] && grep -q VERIFIC-SKIP ${bn}_ref.v; then touch ../${bn}.skip return fi if [ -n "$scriptfiles" ]; then - test_passes $fn $scriptfiles + test_passes -f "$frontend $include_opts" ${bn}_ref.v $scriptfiles elif [ -n "$scriptopt" ]; then - test_passes -f "$frontend" -p "$scriptopt" $fn + test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.v elif [ "$frontend" = "verific" ]; then - test_passes -p "verific -vlog2k $fn; verific -import -all; opt; memory;;" + test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -all; opt; memory;;" elif [ "$frontend" = "verific_gates" ]; then - test_passes -p "verific -vlog2k $fn; verific -import -gates -all; opt; memory;;" + test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -gates -all; opt; memory;;" else - test_passes -f "$frontend" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" $fn - test_passes -f "$frontend" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" $fn + test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v + test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v fi touch ../${bn}.log } diff --git a/tests/tools/cmp_tbdata.c b/tests/tools/cmp_tbdata.c index b81ae1ca..c0b12cd9 100644 --- a/tests/tools/cmp_tbdata.c +++ b/tests/tools/cmp_tbdata.c @@ -4,8 +4,8 @@ #include <string.h> int line = 0; -char buffer1[1024]; -char buffer2[1024]; +char buffer1[8192]; +char buffer2[8192]; void check(bool ok) { |