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* add yosys-docSebastian Kuzminsky2016-04-04
* teach debian to build the docs (manual and presentation)Sebastian Kuzminsky2016-03-28
* build the manual using headers from the source tree, not installedSebastian Kuzminsky2016-03-28
* switch to a free font for the manualSebastian Kuzminsky2016-03-28
* comment the yosys-abc link so I don't remove it againSebastian Kuzminsky2016-03-28
* look for berkeley-abc in the PATHSebastian Kuzminsky2016-03-23
* dch: new UNRELEASED versionSebastian Kuzminsky2016-03-23
* dch: switch from UNRELEASED to unstableSebastian Kuzminsky2016-03-03
* d/control: add Seb to the uploadersSebastian Kuzminsky2016-03-03
* handle yosys-smtbmc's dependency on pythonSebastian Kuzminsky2016-03-03
* add a manpage for yosys-smtbmcSebastian Kuzminsky2016-03-03
* enable parallel compilationSebastian Kuzminsky2016-03-03
* don't run "make" as part of override_dh_auto_configureSebastian Kuzminsky2016-03-03
* fix upstream spelling mistakesSebastian Kuzminsky2016-03-03
* refresh gitrevision patchSebastian Kuzminsky2016-03-03
* update changelog for 0.6-1Sebastian Kuzminsky2016-03-03
* Merge tag 'upstream/0.6' into newSebastian Kuzminsky2016-02-29
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| * Yosys 0.6Clifford Wolf2016-02-26
| * Fixed BLIF parser for empty port assignmentsClifford Wolf2016-02-24
| * Use easyer-to-read unoptimized ceil_log2()Clifford Wolf2016-02-15
| * Updated ABC to ae7d65e71adcClifford Wolf2016-02-15
| * Updated command reference in manualClifford Wolf2016-02-14
| * Changelog for upcoming 0.6 releaseClifford Wolf2016-02-14
| * Fixed more visual studio warningsClifford Wolf2016-02-14
| * Fixed some visual studio warningsClifford Wolf2016-02-13
| * Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2016-02-13
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| | * Fixed MXE ABC buildClifford Wolf2016-02-13
| * | Added "int ceil_log2(int)" functionClifford Wolf2016-02-13
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| * Run dffsr2dff in synth_xilinxClifford Wolf2016-02-13
| * Support for more Verific primitives (patch I got per email)Clifford Wolf2016-02-13
| * Updated ABCClifford Wolf2016-02-08
| * Work around DDR dout sim glitches in ice40 SB_IO sim modelClifford Wolf2016-02-07
| * Updated ABCClifford Wolf2016-02-07
| * Added "stat -liberty" for calculating chip areaClifford Wolf2016-02-04
| * Bugfix in Verific front-endClifford Wolf2016-02-03
| * Updated verific build instructionsClifford Wolf2016-02-02
| * Improved dffsr2dff passClifford Wolf2016-02-02
| * Added dffsr2dffClifford Wolf2016-02-02
| * Added addBufGate module methodClifford Wolf2016-02-02
| * Use alphanumerical order instead of idstring idx in opt_clean compare_signals()Clifford Wolf2016-02-02
| * Added CodeOfConductClifford Wolf2016-02-01
| * Updated ABC to hg rev ee212a9e94dfClifford Wolf2016-02-01
| * Progress in cell library documentationClifford Wolf2016-02-01
| * Added "abc -luts" option, Improved Xilinx logic mappingClifford Wolf2016-02-01
| * Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs)Clifford Wolf2016-02-01
| * SigMap performance improvementClifford Wolf2016-02-01
| * hashlib mfp<> performance improvementsClifford Wolf2016-02-01
| * Added reserve() method to haslib classes andClifford Wolf2016-01-31
| * Merge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosysClifford Wolf2016-01-31
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| | * rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*)Rick Altherr2016-01-31