yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
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\| *	Support for more Verific primitives (patch I got per email)	Clifford Wolf	2016-02-13
\| *	Updated ABC	Clifford Wolf	2016-02-08
\| *	Work around DDR dout sim glitches in ice40 SB_IO sim model	Clifford Wolf	2016-02-07
\| *	Updated ABC	Clifford Wolf	2016-02-07
\| *	Added "stat -liberty" for calculating chip area	Clifford Wolf	2016-02-04
\| *	Bugfix in Verific front-end	Clifford Wolf	2016-02-03
\| *	Updated verific build instructions	Clifford Wolf	2016-02-02
\| *	Improved dffsr2dff pass	Clifford Wolf	2016-02-02
\| *	Added dffsr2dff	Clifford Wolf	2016-02-02
\| *	Added addBufGate module method	Clifford Wolf	2016-02-02
\| *	Use alphanumerical order instead of idstring idx in opt_clean compare_signals()	Clifford Wolf	2016-02-02
\| *	Added CodeOfConduct	Clifford Wolf	2016-02-01
\| *	Updated ABC to hg rev ee212a9e94df	Clifford Wolf	2016-02-01
\| *	Progress in cell library documentation	Clifford Wolf	2016-02-01
\| *	Added "abc -luts" option, Improved Xilinx logic mapping	Clifford Wolf	2016-02-01
\| *	Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs)	Clifford Wolf	2016-02-01
\| *	SigMap performance improvement	Clifford Wolf	2016-02-01
\| *	hashlib mfp<> performance improvements	Clifford Wolf	2016-02-01
\| *	Added reserve() method to haslib classes and	Clifford Wolf	2016-01-31
\| *	Merge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosys	Clifford Wolf	2016-01-31
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\| \| *	rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*)	Rick Altherr	2016-01-31
\| \| *	rtlil: speed up SigSpec::sort_and_unify()	Rick Altherr	2016-01-31
\| \| *	rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*)	Rick Altherr	2016-01-31
\| \| *	genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSi...	Rick Altherr	2016-01-31
\| \| *	rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*)	Rick Altherr	2016-01-31
\| * \|	More clang sanitizer stuff	Clifford Wolf	2016-01-31
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\| *	Meaningless coding style change	Clifford Wolf	2016-01-31
\| *	Merge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosys	Clifford Wolf	2016-01-31
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\| \| *	rtlil: rewrite remove2() to avoid copying	Rick Altherr	2016-01-30
\| \| *	rtlil: duplicate remove2() for std::set<>	Rick Altherr	2016-01-29
\| \| *	rtlil: change IdString comparison operators to take references instead of copies	Rick Altherr	2016-01-29
\| * \|	Addedd clang sanitizers	Clifford Wolf	2016-01-31
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\| *	Added "equiv_struct -fwonly"	Clifford Wolf	2016-01-08
\| *	Bugfixes in equiv_struct	Clifford Wolf	2016-01-08
\| *	Added "submod -copy"	Clifford Wolf	2016-01-08
\| *	Added "write_blif -cname" mode	Clifford Wolf	2016-01-06
\| *	Added "equiv_struct -maxiter <N>"	Clifford Wolf	2016-01-06
\| *	Added "equiv_add -try" mode	Clifford Wolf	2016-01-06
\| *	Fixed "splitnets -ports" for hierarchical designs	Clifford Wolf	2015-12-22
\| *	Re-run ice40_opt in "synth_ice40 -abc2"	Clifford Wolf	2015-12-22
\| *	Improvements in ice40_opt	Clifford Wolf	2015-12-22
\| *	Bugfix in ice40_ffinit	Clifford Wolf	2015-12-22
\| *	Improved ice40_ffinit	Clifford Wolf	2015-12-22
\| *	Run opt_const before check in default scripts	Clifford Wolf	2015-12-22
\| *	Added %R select expression	Clifford Wolf	2015-12-20
\| *	Various improvements in BLIF front-end	Clifford Wolf	2015-12-20
\| *	Added yosys-smtbmc -S	Clifford Wolf	2015-12-20
\| *	Merge pull request #110 from scanlime/master	Clifford Wolf	2015-12-15
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\| \| *	Mac build fix, gsed -> sed	Micah Elizabeth Scott	2015-12-15
\| \| *	Remove nonportable "-r" option from xargs	Micah Elizabeth Scott	2015-12-15
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