yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Fixed width and sign detection for ** operator	Clifford Wolf	2013-08-19
*	Added support for bufif0/bufif1 primitives	Clifford Wolf	2013-08-19
*	Improved ast dumping (ast/verilog frontend)	Clifford Wolf	2013-08-19
*	Implemented same div-by-zero behavior as found in other synthesis tools	Clifford Wolf	2013-08-15
*	Fixed signed div/mod in const eval (rounding and stuff)	Clifford Wolf	2013-08-15
*	Added ezsat api for creation of anonymous vectors	Clifford Wolf	2013-08-15
*	Added sat -ignore_div_by_zero switch	Clifford Wolf	2013-08-15
*	Added eval -brute_force_equiv_checker_x mode	Clifford Wolf	2013-08-15
*	Added support for "2**n" shifter encoding	Clifford Wolf	2013-08-12
*	Added SAT support for $div and $mod cells	Clifford Wolf	2013-08-11
*	Added "clean -purge" and ";;;" support	Clifford Wolf	2013-08-11
*	Added ";;" as shortcut for "; clean;"	Clifford Wolf	2013-08-11
*	freduce performance fix	Clifford Wolf	2013-08-10
*	Added $div and $mod technology mapping	Clifford Wolf	2013-08-09
*	Added techmap -opt mode	Clifford Wolf	2013-08-09
*	Some fixes to improve determinism	Clifford Wolf	2013-08-09
*	Sort ctrl signals in fsm_extract	Clifford Wolf	2013-08-08
*	Added -try option to freduce pass	Clifford Wolf	2013-08-08
*	Added "clean" command (less verbose opt_clean)	Clifford Wolf	2013-08-08
*	Fixed topological ordering in freduce pass	Clifford Wolf	2013-08-07
*	Improved handling of private names in opt_clean and rename commands	Clifford Wolf	2013-08-07
*	Added stubnets example to manual prog chapter	Clifford Wolf	2013-08-07
*	Small bugfixes in freduce pass	Clifford Wolf	2013-08-06
*	Added freduce command	Clifford Wolf	2013-08-06
*	Fixed SigPool::del() method	Clifford Wolf	2013-08-06
*	Added proper deallocation of history buffer	Clifford Wolf	2013-08-06
*	Updated TODO section in README	Clifford Wolf	2013-08-01
*	Added "design" command (-reset, -save, -load)	Clifford Wolf	2013-07-27
*	Added "help -write-web-command-reference-manual"	Clifford Wolf	2013-07-26
*	Fixed comments in manual rtlil/ilang syntax	Clifford Wolf	2013-07-25
*	Added RTLIL and Liberty syntax highlighting to manual	Clifford Wolf	2013-07-25
*	Automatically run "proc" on extract map files	Clifford Wolf	2013-07-24
*	Added $lut cells and abc lut mapping support	Clifford Wolf	2013-07-23
*	Fixed "make clean" for manual files	Clifford Wolf	2013-07-23
*	Added web site link to README	Clifford Wolf	2013-07-21
*	Added Yosys Manual	Clifford Wolf	2013-07-20
*	More fixes in ternary op sign handling	Clifford Wolf	2013-07-12
*	Fixed sign handling in ternary operator	Clifford Wolf	2013-07-12
*	Added ast frontend refactoring to TODO	Clifford Wolf	2013-07-11
*	Another vloghammer related bugfix	Clifford Wolf	2013-07-11
*	Bugfixes for empty signal vectors	Clifford Wolf	2013-07-10
*	Fixed sign propagation in bit-wise operators	Clifford Wolf	2013-07-09
*	More fixes in ast expression sign/width handling	Clifford Wolf	2013-07-09
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-07-09
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\| *	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09
* \|	Fixed shift ops with large right hand side	Clifford Wolf	2013-07-09
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*	Fixed another bug found using vloghammer	Clifford Wolf	2013-07-07
*	Fixed AST_CONSTANT node generation	Clifford Wolf	2013-07-07
*	Removed tests/xsthammer	Clifford Wolf	2013-07-07
*	Added opt_clean -purge option	Clifford Wolf	2013-07-07