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* Fixed AST handling of variables declared inside a functions main blockClifford Wolf2014-08-05
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* Added "show -signed"Clifford Wolf2014-08-04
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* Added support for non-standard "module mod_name(...);" syntaxClifford Wolf2014-08-04
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* Added RTLIL::IdString::in(...)Clifford Wolf2014-08-04
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* Fixed "share" for memory read portsClifford Wolf2014-08-03
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* Added "wreduce" to some of the standard test benchesClifford Wolf2014-08-03
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* Progress in "wreduce" passClifford Wolf2014-08-03
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* Added "wreduce" command (work in progress)Clifford Wolf2014-08-03
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* Added query() API to ModIndexClifford Wolf2014-08-03
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* Added ID() macro for static IdStringsClifford Wolf2014-08-03
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* Implemented recursive techmapClifford Wolf2014-08-03
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* Fixes in show command (related to new IdString)Clifford Wolf2014-08-03
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* Implemented simplemap support for "techmap -extern"Clifford Wolf2014-08-02
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* Fixed a va_list corruption in logv_error()Clifford Wolf2014-08-02
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* Be more conservative with printing decimal numbers in verilog backendClifford Wolf2014-08-02
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* Improved verilog output for ordinary $mux cellsClifford Wolf2014-08-02
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* Bugfix in "techmap -extern"Clifford Wolf2014-08-02
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* Removed at() method from RTLIL::IdStringClifford Wolf2014-08-02
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* No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
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* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-02
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* Limit size of log_signal buffer to 100 elementsClifford Wolf2014-08-02
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* Improvements in new RTLIL::IdString implementationClifford Wolf2014-08-02
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* Fixed a performance bug in opt_reduceClifford Wolf2014-08-02
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* Implemented new reference counting RTLIL::IdStringClifford Wolf2014-08-02
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* Fixed memory corruption related to id2cstr()Clifford Wolf2014-08-02
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* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
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* Preparations for RTLIL::IdString redesign: cleanup of existing codeClifford Wolf2014-08-02
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* Added logfile hash to statistics footerClifford Wolf2014-08-01
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* Replaced sha1 implementationClifford Wolf2014-08-01
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* Added per-pass cpu usage statisticsClifford Wolf2014-08-01
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* Added ModIndex helper class, some changes to RTLIL::MonitorClifford Wolf2014-08-01
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* Packed SigBit::data and SigBit::offset in a unionClifford Wolf2014-08-01
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* Consolidated hana test benches into fewer filesClifford Wolf2014-08-01
| | | | | | | | for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \ ${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done; ..etc..
* Added "test_autotb -n <num_iter>" optionClifford Wolf2014-08-01
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* Renamed modwalker.h to modtools.hClifford Wolf2014-07-31
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* Various cleanups in Makefile, Renamed default configurationsClifford Wolf2014-07-31
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* Added compiler + compiler version + compiler flags to version stringClifford Wolf2014-07-31
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* Fixed build of verific bindingsClifford Wolf2014-07-31
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
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* Added "trace" commandClifford Wolf2014-07-31
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* Added RTLIL::MonitorClifford Wolf2014-07-31
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* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
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* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
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* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-31
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* Added "techmap -assert"Clifford Wolf2014-07-31
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* Reorganized stdcells.v (no actual code change, just moved and indented stuff)Clifford Wolf2014-07-31
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* Added "yosys -A"Clifford Wolf2014-07-31
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* Added "yosys -Q"Clifford Wolf2014-07-31
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* Added techmap CONSTMAP featureClifford Wolf2014-07-30
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* Fixed counting verilog line numbers for "// synopsys translate_off" sectionsClifford Wolf2014-07-30
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