Commit message (Expand)AuthorAge
* Added "maccmap" commandClifford Wolf2014-09-07
* Added "test_cell -nosat"Clifford Wolf2014-09-07
* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-06
* Added $macc eval modelClifford Wolf2014-09-06
* Added $macc SAT modelClifford Wolf2014-09-06
* Fixed $clog2 (off by one error)Clifford Wolf2014-09-06
* Added $macc simlib model (also use as techmap rule for now)Clifford Wolf2014-09-06
* Fixed assignment of out-of bounds array elementClifford Wolf2014-09-06
* Added $macc cell typeClifford Wolf2014-09-06
* Fixed autotest for non-basename argumentsClifford Wolf2014-09-06
* Merge branch 'master' of Wolf2014-09-06
| * Merge pull request #38 from rubund/masterClifford Wolf2014-09-06
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| | * Corrected spelling mistakes found by lintianRuben Undheim2014-09-06
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| * Added tests/various/constmsk_test.ysClifford Wolf2014-09-04
* | Added "test_cell -script"Clifford Wolf2014-09-06
* Fixed "opt_const -fine" for $pos cellsClifford Wolf2014-09-04
* Removed $bu0 cell typeClifford Wolf2014-09-04
* Using $pos models for $bu0Clifford Wolf2014-09-03
* Fixed "test_cells -vlog"Clifford Wolf2014-09-03
* Fixes in $alu SAT- and eval-modelsClifford Wolf2014-09-03
* Undef-related fixes in simlib $alu modelClifford Wolf2014-09-02
* Improvements in "test_cell -vlog"Clifford Wolf2014-09-02
* Added test_cell -vlogClifford Wolf2014-09-02
* Create a default selection stack in RTLIL::Design::Design()Clifford Wolf2014-09-02
* Small bug fixes in $not, $neg, and $shiftx modelsClifford Wolf2014-09-02
* Added SAT testing to test_cell eval stageClifford Wolf2014-09-02
* Removed references to yosys-svgviewer from docsClifford Wolf2014-09-02
* Removed yosys-svgviewerClifford Wolf2014-09-02
* Using "xdot" instead of "yosys-svgviewer" in show commandClifford Wolf2014-09-02
* Added $alu support to test_cellClifford Wolf2014-09-01
* Added ConstEval model for $alu cellsClifford Wolf2014-09-01
* Added SAT model for $alu cellsClifford Wolf2014-09-01
* Fixed "test_cell -simlib all"Clifford Wolf2014-09-01
* Added "test_cell -simlib -v"Clifford Wolf2014-09-01
* Added "techmap -autoproc"Clifford Wolf2014-09-01
* Fixes in old SAT example.ysClifford Wolf2014-09-01
* Moved "share" and "wreduce" to passes/opt/Clifford Wolf2014-09-01
* Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...Clifford Wolf2014-09-01
* Added eval testing to test_cellClifford Wolf2014-08-31
* Fixed return size of const_*() eval functionsClifford Wolf2014-08-31
* Added RTLIL::Const::size()Clifford Wolf2014-08-31
* Added eval model for $lut cellsClifford Wolf2014-08-31
* Typo fixes in cell->*Param() APIClifford Wolf2014-08-31
* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-31
* Added design->scratchpadClifford Wolf2014-08-30
* Added $alu cell typeClifford Wolf2014-08-30
* Added autotest -e (do not use -noexpr on write_verilog)Clifford Wolf2014-08-30
* Improved write address decoder generation memory_mapClifford Wolf2014-08-30
* Fixed module->addPmux()Clifford Wolf2014-08-30
* Using worker class in memory_mapClifford Wolf2014-08-30