yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02
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*	Added opt_const -clkinv	Clifford Wolf	2015-07-01
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*	Added logic-loop error handling to freduce	Clifford Wolf	2015-06-30
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2015-06-30
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\| *	Added YosysJS.create_worker()	Clifford Wolf	2015-06-28
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* \|	Bugfix in chparam	Clifford Wolf	2015-06-30
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* \|	Added design->rename(module, new_name)	Clifford Wolf	2015-06-30
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*	iCE40: set min bram efficiency to 2%	Clifford Wolf	2015-06-20
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*	Using static mem size of 128 MB in emcc build	Clifford Wolf	2015-06-20
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*	Added init support to SMV back-end	Clifford Wolf	2015-06-19
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*	Progress in SMV back-end	Clifford Wolf	2015-06-19
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*	Progress in SMV back-end	Clifford Wolf	2015-06-19
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*	Progress in SMV back-end	Clifford Wolf	2015-06-18
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*	Progress in SMV back-end	Clifford Wolf	2015-06-17
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*	Added "rename -top new_name"	Clifford Wolf	2015-06-17
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*	Progress in SMV back-end	Clifford Wolf	2015-06-17
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*	Progress in SMV back-end	Clifford Wolf	2015-06-16
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*	Added "synth -nordff -noalumacc"	Clifford Wolf	2015-06-15
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*	Progress in SMV back-end	Clifford Wolf	2015-06-15
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*	Progress in SMV back-end	Clifford Wolf	2015-06-15
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*	Added "write_smv" skeleton	Clifford Wolf	2015-06-15
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*	Removed debug code from write_smt2	Clifford Wolf	2015-06-14
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*	Modernized memory_dff (and fixed a bug)	Clifford Wolf	2015-06-14
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*	Added "memory -nordff"	Clifford Wolf	2015-06-14
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*	Added write_smt2 -mem	Clifford Wolf	2015-06-14
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*	Makefile fix for YosysJS build	Clifford Wolf	2015-06-11
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*	Fixed cstr_buf for std::string with small string optimization	Clifford Wolf	2015-06-11
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*	Improvements in cellaigs.cc and "json -aig"	Clifford Wolf	2015-06-11
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*	AigMaker refactoring	Clifford Wolf	2015-06-10
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*	Added "json -aig"	Clifford Wolf	2015-06-10
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*	Renamed "aig" to "aigmap"	Clifford Wolf	2015-06-10
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*	Fixed cellaigs port extending	Clifford Wolf	2015-06-10
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*	Added "aig" pass	Clifford Wolf	2015-06-09
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*	synth_ice40 now flattens by default	Clifford Wolf	2015-06-09
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*	Added cellaigs API	Clifford Wolf	2015-06-09
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*	Merge clock inverters in memory_dff	Clifford Wolf	2015-06-09
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*	Merge branch 'verilog-backend-memV2' of github.com:wluker/yosys	Clifford Wolf	2015-06-09
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\| *	$mem cell in verilog backend : grouped writes by clock	luke whittlesey	2015-06-08
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\| *	Bug fix in $mem verilog backend + changed tests/bram flow of make test.	luke whittlesey	2015-06-04
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* \|	Fixed "avail_parameters" handling in module clone/copy	Clifford Wolf	2015-06-08
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* \|	Added log_dump() support for IdStrings	Clifford Wolf	2015-06-08
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* \|	Fixed handling of parameters with reversed range	Clifford Wolf	2015-06-08
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*	Added opt_share -share_all	Clifford Wolf	2015-05-31
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*	Added iCE40 PLL cells	Clifford Wolf	2015-05-31
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*	Added liberty dont_use support to dfflibmap	Clifford Wolf	2015-05-31
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*	Fixed signedness of genvar expressions	Clifford Wolf	2015-05-29
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*	Added output args to synth_ice40	Clifford Wolf	2015-05-26
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*	Improvements in BLIF front-end	Clifford Wolf	2015-05-24
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*	improved ice40 SB_IO sim model	Clifford Wolf	2015-05-23
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*	Improved "flatten" handlings of inout ports	Clifford Wolf	2015-05-23
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