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* Xilinx mojo_counter example is now workingClifford Wolf2013-10-27
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* Fixed hex string generation bug in edif backendClifford Wolf2013-10-27
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* Renamed techlibs/xilinx7 to techlibs/xilinxClifford Wolf2013-10-26
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* Improved xilinx mojo_counter exampleClifford Wolf2013-10-26
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* Added support for i/o buffers to iopadmapClifford Wolf2013-10-26
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* Added another xilinx example (not funcional yet)Clifford Wolf2013-10-26
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* Added support for sr flip-flops to dfflibmapClifford Wolf2013-10-24
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* Added support for complex set-reset flip-flops in proc_dffClifford Wolf2013-10-24
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* Fixed handling of boolean attributes (passes)Clifford Wolf2013-10-24
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* Fixed handling of boolean attributes (backends)Clifford Wolf2013-10-24
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* Fixed handling of boolean attributes (frontends)Clifford Wolf2013-10-24
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* Fixed handling of boolean attributes (kernel)Clifford Wolf2013-10-24
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* Fixed parsing of value-less attributes in ilangClifford Wolf2013-10-23
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* Improved handling of dff with async resetsClifford Wolf2013-10-21
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* Added handling of multiple async paths in proc_arstClifford Wolf2013-10-19
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* Changed NEW_WIRE API to return the wire, not the signalClifford Wolf2013-10-18
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* Added dffsr support to proc_dff passClifford Wolf2013-10-18
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* Added RTLIL NEW_WIRE macroClifford Wolf2013-10-18
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* Bugfix in dffsr techmap rulesClifford Wolf2013-10-18
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* Added techmap rules for $sr, $dffsr and $dlatchClifford Wolf2013-10-18
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* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-18
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* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-18
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* Improved way of connecting ports in techmap passClifford Wolf2013-10-17
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* Only prefer connected signals iff they have public namesClifford Wolf2013-10-17
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* Added -buf, -true and -false options to blif backendClifford Wolf2013-10-17
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* Fixed bug in synthesis of memories that are never writtenClifford Wolf2013-10-17
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* Avoid re-arranging signals on register outputsClifford Wolf2013-10-17
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* Fixed detection of major wires in opt_cleanClifford Wolf2013-10-17
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* Added iopadmap passClifford Wolf2013-10-16
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* Moved dfflibmap from passes/dfflibmap to passes/techmapClifford Wolf2013-10-16
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* Added map, par and bitgen to xlinx7 exampleClifford Wolf2013-10-16
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* Fixed parsing or liberty file statements such as 'clocked_on : "(!CLK)";'Clifford Wolf2013-10-16
| | | | Patch by Tim Edwards
* Added recommended apt-get commands to READMEClifford Wolf2013-10-11
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* Fixed minisat includeClifford Wolf2013-10-11
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* Pinned ABC revision to 0f9e5488ced3Clifford Wolf2013-10-03
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* Improvements in EDIF backendClifford Wolf2013-09-17
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* Added additional options to BLIF backendClifford Wolf2013-09-15
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* Added BLIF backendClifford Wolf2013-09-15
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* A couple of small fixes in SPICE backendClifford Wolf2013-09-15
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* Moved common techlib files to techlibs/commonClifford Wolf2013-09-15
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* Updated manualClifford Wolf2013-09-15
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* Added spice testbench to techlibs/cmosClifford Wolf2013-09-14
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* Added spice backendClifford Wolf2013-09-14
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-09-03
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| * Encode large (>32 bits) parameters as hex string in edif backendClifford Wolf2013-08-28
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| * Improved edif backendClifford Wolf2013-08-27
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| * Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)Clifford Wolf2013-08-27
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* | Added -selected option to various backendsClifford Wolf2013-09-03
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* Added simple xilinx7 technology mapping filesClifford Wolf2013-08-22
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* More explicit integer output in verilog backendClifford Wolf2013-08-22
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