yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Added DFFSR cell to techlibs/cmos/cmos_cells.lib	Clifford Wolf	2013-10-31
*	Added placeholder check to dfflibmap and cleaned up some other placeholder ch...	Clifford Wolf	2013-10-31
*	Changed MiniSAT feater defines again	Clifford Wolf	2013-10-31
*	Added paragraph to README file to avoid mycells.lib confusion	Clifford Wolf	2013-10-31
*	README file typo fix	Clifford Wolf	2013-10-31
*	Some additions to the README file	Clifford Wolf	2013-10-31
*	Fixed ezminisat C++ errors: undef PRIi64	Clifford Wolf	2013-10-30
*	Added detection for endless recursion in fsm_detect pass	Clifford Wolf	2013-10-30
*	Fixed help message typo (memory pass)	Clifford Wolf	2013-10-30
*	Added -format option to splitnets	Clifford Wolf	2013-10-29
*	Merge pull request #12 from jameswalmsley/master	Clifford Wolf	2013-10-27
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\| *	[EXAMPLES] Ported the mojo counter example to Zynq ZED board.	James Walmsley	2013-10-27
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*	Fixed get_share_file_name() for installed yosys	Clifford Wolf	2013-10-27
*	Cleanups in xilinx examples	Clifford Wolf	2013-10-27
*	Added synth_xilinx command	Clifford Wolf	2013-10-27
*	Added API and Makefile rules for share/ files	Clifford Wolf	2013-10-27
*	Added design->full_selection() helper method	Clifford Wolf	2013-10-27
*	Moved simple xilinx counter sim example to subdir	Clifford Wolf	2013-10-27
*	Xilinx mojo_counter example is now working	Clifford Wolf	2013-10-27
*	Fixed hex string generation bug in edif backend	Clifford Wolf	2013-10-27
*	Renamed techlibs/xilinx7 to techlibs/xilinx	Clifford Wolf	2013-10-26
*	Improved xilinx mojo_counter example	Clifford Wolf	2013-10-26
*	Added support for i/o buffers to iopadmap	Clifford Wolf	2013-10-26
*	Added another xilinx example (not funcional yet)	Clifford Wolf	2013-10-26
*	Added support for sr flip-flops to dfflibmap	Clifford Wolf	2013-10-24
*	Added support for complex set-reset flip-flops in proc_dff	Clifford Wolf	2013-10-24
*	Fixed handling of boolean attributes (passes)	Clifford Wolf	2013-10-24
*	Fixed handling of boolean attributes (backends)	Clifford Wolf	2013-10-24
*	Fixed handling of boolean attributes (frontends)	Clifford Wolf	2013-10-24
*	Fixed handling of boolean attributes (kernel)	Clifford Wolf	2013-10-24
*	Fixed parsing of value-less attributes in ilang	Clifford Wolf	2013-10-23
*	Improved handling of dff with async resets	Clifford Wolf	2013-10-21
*	Added handling of multiple async paths in proc_arst	Clifford Wolf	2013-10-19
*	Changed NEW_WIRE API to return the wire, not the signal	Clifford Wolf	2013-10-18
*	Added dffsr support to proc_dff pass	Clifford Wolf	2013-10-18
*	Added RTLIL NEW_WIRE macro	Clifford Wolf	2013-10-18
*	Bugfix in dffsr techmap rules	Clifford Wolf	2013-10-18
*	Added techmap rules for $sr, $dffsr and $dlatch	Clifford Wolf	2013-10-18
*	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	Clifford Wolf	2013-10-18
*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18
*	Improved way of connecting ports in techmap pass	Clifford Wolf	2013-10-17
*	Only prefer connected signals iff they have public names	Clifford Wolf	2013-10-17
*	Added -buf, -true and -false options to blif backend	Clifford Wolf	2013-10-17
*	Fixed bug in synthesis of memories that are never written	Clifford Wolf	2013-10-17
*	Avoid re-arranging signals on register outputs	Clifford Wolf	2013-10-17
*	Fixed detection of major wires in opt_clean	Clifford Wolf	2013-10-17
*	Added iopadmap pass	Clifford Wolf	2013-10-16
*	Moved dfflibmap from passes/dfflibmap to passes/techmap	Clifford Wolf	2013-10-16
*	Added map, par and bitgen to xlinx7 example	Clifford Wolf	2013-10-16
*	Fixed parsing or liberty file statements such as 'clocked_on : "(!CLK)";'	Clifford Wolf	2013-10-16