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* Added "show -signed"Clifford Wolf2014-08-04
* Added support for non-standard "module mod_name(...);" syntaxClifford Wolf2014-08-04
* Added RTLIL::IdString::in(...)Clifford Wolf2014-08-04
* Fixed "share" for memory read portsClifford Wolf2014-08-03
* Added "wreduce" to some of the standard test benchesClifford Wolf2014-08-03
* Progress in "wreduce" passClifford Wolf2014-08-03
* Added "wreduce" command (work in progress)Clifford Wolf2014-08-03
* Added query() API to ModIndexClifford Wolf2014-08-03
* Added ID() macro for static IdStringsClifford Wolf2014-08-03
* Implemented recursive techmapClifford Wolf2014-08-03
* Fixes in show command (related to new IdString)Clifford Wolf2014-08-03
* Implemented simplemap support for "techmap -extern"Clifford Wolf2014-08-02
* Fixed a va_list corruption in logv_error()Clifford Wolf2014-08-02
* Be more conservative with printing decimal numbers in verilog backendClifford Wolf2014-08-02
* Improved verilog output for ordinary $mux cellsClifford Wolf2014-08-02
* Bugfix in "techmap -extern"Clifford Wolf2014-08-02
* Removed at() method from RTLIL::IdStringClifford Wolf2014-08-02
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-02
* Limit size of log_signal buffer to 100 elementsClifford Wolf2014-08-02
* Improvements in new RTLIL::IdString implementationClifford Wolf2014-08-02
* Fixed a performance bug in opt_reduceClifford Wolf2014-08-02
* Implemented new reference counting RTLIL::IdStringClifford Wolf2014-08-02
* Fixed memory corruption related to id2cstr()Clifford Wolf2014-08-02
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Preparations for RTLIL::IdString redesign: cleanup of existing codeClifford Wolf2014-08-02
* Added logfile hash to statistics footerClifford Wolf2014-08-01
* Replaced sha1 implementationClifford Wolf2014-08-01
* Added per-pass cpu usage statisticsClifford Wolf2014-08-01
* Added ModIndex helper class, some changes to RTLIL::MonitorClifford Wolf2014-08-01
* Packed SigBit::data and SigBit::offset in a unionClifford Wolf2014-08-01
* Consolidated hana test benches into fewer filesClifford Wolf2014-08-01
* Added "test_autotb -n <num_iter>" optionClifford Wolf2014-08-01
* Renamed modwalker.h to modtools.hClifford Wolf2014-07-31
* Various cleanups in Makefile, Renamed default configurationsClifford Wolf2014-07-31
* Added compiler + compiler version + compiler flags to version stringClifford Wolf2014-07-31
* Fixed build of verific bindingsClifford Wolf2014-07-31
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Added "trace" commandClifford Wolf2014-07-31
* Added RTLIL::MonitorClifford Wolf2014-07-31
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-31
* Added "techmap -assert"Clifford Wolf2014-07-31
* Reorganized stdcells.v (no actual code change, just moved and indented stuff)Clifford Wolf2014-07-31
* Added "yosys -A"Clifford Wolf2014-07-31
* Added "yosys -Q"Clifford Wolf2014-07-31
* Added techmap CONSTMAP featureClifford Wolf2014-07-30
* Fixed counting verilog line numbers for "// synopsys translate_off" sectionsClifford Wolf2014-07-30
* Added write_file commandClifford Wolf2014-07-30