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* Added passing of various options to vhdl2verilogClifford Wolf2014-07-12
* Use "verilog -sv" to parse .sv filesClifford Wolf2014-07-11
* Fixed processing of initial values for block-local variablesClifford Wolf2014-07-11
* now ignore init attributes on non-register wires in sat commandClifford Wolf2014-07-05
* fixed parsing of constant with comment between size and valueClifford Wolf2014-07-02
* small changes in presentationClifford Wolf2014-07-02
* Tiny fix in presentationClifford Wolf2014-06-29
* Progress in presentationClifford Wolf2014-06-29
* Added links to some liberty files to READMEClifford Wolf2014-06-28
* Progress in presentationClifford Wolf2014-06-26
* Fixed handling of mixed real/int ternary expressionsClifford Wolf2014-06-25
* More found_real-related fixes to AstNode::detectSignWidthWorkerClifford Wolf2014-06-24
* Progress in presentationClifford Wolf2014-06-22
* Little steps in realmath test benchClifford Wolf2014-06-21
* fixed signdness detection for expressions with realsClifford Wolf2014-06-21
* fixed typoClifford Wolf2014-06-21
* Progress in presentationClifford Wolf2014-06-21
* Do not create $dffsr cells with no-op resets in proc_dffClifford Wolf2014-06-19
* Added test case for AstNode::MEM2REG_FL_CMPLX_LHSClifford Wolf2014-06-17
* Added AstNode::MEM2REG_FL_CMPLX_LHSClifford Wolf2014-06-17
* Improved handling of relational op of real valuesClifford Wolf2014-06-17
* Little steps in realmath test benchClifford Wolf2014-06-16
* Improved ternary support for real valuesClifford Wolf2014-06-16
* Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012Clifford Wolf2014-06-16
* Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)Clifford Wolf2014-06-16
* Added found_real feature to AstNode::detectSignWidthClifford Wolf2014-06-16
* Added more calls to "hierarchy" to README fileClifford Wolf2014-06-15
* Removed long running tests from tests/simple/realexpr.v (replaced by tests/re...Clifford Wolf2014-06-15
* Added tests/realmath to "make test"Clifford Wolf2014-06-15
* Improved AstNode::realAsConst for large numbersClifford Wolf2014-06-15
* Improved realmath test benchClifford Wolf2014-06-15
* Improved parsing of large integer constantsClifford Wolf2014-06-15
* Improved AstNode::asReal for large integersClifford Wolf2014-06-15
* improved realmath test benchClifford Wolf2014-06-14
* improved (fixed) conversion of real values to bit vectorsClifford Wolf2014-06-14
* progress in realmath test benchClifford Wolf2014-06-14
* Fixed relational operators for const real expressionsClifford Wolf2014-06-14
* added first draft of real math testcase generatorClifford Wolf2014-06-14
* Progress in presentationClifford Wolf2014-06-14
* Added %D and %c select commandsClifford Wolf2014-06-14
* Added support for math functionsClifford Wolf2014-06-14
* Added realexpr.v test caseClifford Wolf2014-06-14
* Added handling of real-valued parameters/localparamsClifford Wolf2014-06-14
* Implemented more real arithmeticClifford Wolf2014-06-14
* Implemented basic real arithmeticClifford Wolf2014-06-14
* Added real->int convertion in ast genrtlilClifford Wolf2014-06-14
* Added Verilog lexer and parser support for real valuesClifford Wolf2014-06-13
* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-12
* Now we are in Yoys 0.3.0+ developmentClifford Wolf2014-06-08
* Tagging Yosys 0.3.0Clifford Wolf2014-06-08