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* Fixed SigPool::del() methodClifford Wolf2013-08-06
* Added proper deallocation of history bufferClifford Wolf2013-08-06
* Updated TODO section in READMEClifford Wolf2013-08-01
* Added "design" command (-reset, -save, -load)Clifford Wolf2013-07-27
* Added "help -write-web-command-reference-manual"Clifford Wolf2013-07-26
* Fixed comments in manual rtlil/ilang syntaxClifford Wolf2013-07-25
* Added RTLIL and Liberty syntax highlighting to manualClifford Wolf2013-07-25
* Automatically run "proc" on extract map filesClifford Wolf2013-07-24
* Added $lut cells and abc lut mapping supportClifford Wolf2013-07-23
* Fixed "make clean" for manual filesClifford Wolf2013-07-23
* Added web site link to READMEClifford Wolf2013-07-21
* Added Yosys ManualClifford Wolf2013-07-20
* More fixes in ternary op sign handlingClifford Wolf2013-07-12
* Fixed sign handling in ternary operatorClifford Wolf2013-07-12
* Added ast frontend refactoring to TODOClifford Wolf2013-07-11
* Another vloghammer related bugfixClifford Wolf2013-07-11
* Bugfixes for empty signal vectorsClifford Wolf2013-07-10
* Fixed sign propagation in bit-wise operatorsClifford Wolf2013-07-09
* More fixes in ast expression sign/width handlingClifford Wolf2013-07-09
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-07-09
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| * Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-09
* | Fixed shift ops with large right hand sideClifford Wolf2013-07-09
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* Fixed another bug found using vloghammerClifford Wolf2013-07-07
* Fixed AST_CONSTANT node generationClifford Wolf2013-07-07
* Removed tests/xsthammerClifford Wolf2013-07-07
* Added opt_clean -purge optionClifford Wolf2013-07-07
* Fixed handling of $eq and $ne in opt_constClifford Wolf2013-07-07
* Fixed vivado related xsthammer bugsClifford Wolf2013-07-05
* Various improvements in xsthammer report generatorClifford Wolf2013-07-05
* Added work-around to isim bug in xsthammer report scriptClifford Wolf2013-07-05
* Fixed gcc warnings in ezminisatClifford Wolf2013-07-05
* Added CARRY4 Xilinx cell to xsthammer cell libClifford Wolf2013-07-05
* Added xsthammer report generatorClifford Wolf2013-07-05
* Improved xsthammer quartus supportClifford Wolf2013-07-04
* Added Altera Cyclon III cell library to xsthammerClifford Wolf2013-07-04
* Documentation updatesClifford Wolf2013-07-04
* Added defparam support to Verilog/AST frontendClifford Wolf2013-07-04
* Added QMAKE makefile variableClifford Wolf2013-07-03
* Added Altera Quartus support to xsthammerClifford Wolf2013-07-03
* Progress in xsthammerClifford Wolf2013-07-03
* Added vivado support to xsthammerClifford Wolf2013-06-26
* Added SAT support for -all/-max with -verifyClifford Wolf2013-06-23
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-06-20
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| * Added renaming of wires and cells to "rename" commandClifford Wolf2013-06-19
* | Added timout functionality to SAT solverClifford Wolf2013-06-20
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* Added "eval" passClifford Wolf2013-06-19
* Fixed build with clangClifford Wolf2013-06-18
* Added splitnets commandClifford Wolf2013-06-18
* Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() APIClifford Wolf2013-06-18
* Added more stuff to xsthammer, found first xst bugClifford Wolf2013-06-17