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* Updated READMEClifford Wolf2014-04-18
* Merge pull request #33 from bentley/doxClifford Wolf2014-04-11
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| * Typos and grammar fixes through chapter 2.Anthony J. Bentley2014-04-11
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* Merge pull request #31 from bentley/posix-rmClifford Wolf2014-04-05
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| * POSIX find requires a path argument.Anthony J. Bentley2014-04-04
| * Remove non-POSIX 'rm -v'.Anthony J. Bentley2014-04-04
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* Added SIMLIB_NOLUT to simlib.vClifford Wolf2014-04-02
* Added SIMLIB_NOSR to simlib.vClifford Wolf2014-04-02
* Added support for dlatchsr cellsClifford Wolf2014-03-31
* Fixed mapping of Verific WIDE_DFFRS operatorClifford Wolf2014-03-20
* Fixed mapping of Verific FADD primitive with unconnected outputsClifford Wolf2014-03-20
* Fixed performance problem in opt_mux with nets driven by many conflicting dri...Clifford Wolf2014-03-19
* Progress in Verific bindingsClifford Wolf2014-03-17
* Fixed typo in RTLIL::Module::addAdff()Clifford Wolf2014-03-17
* Progress in Verific bindingsClifford Wolf2014-03-17
* Progress in Verific bindingsClifford Wolf2014-03-17
* Added support for memories to verific bindingsClifford Wolf2014-03-16
* Use Verific Net::{IsGnd,IsPwr} API in Verific bindingsClifford Wolf2014-03-16
* Fixed typo in RTLIL::Module::{addSshl,addSshr}Clifford Wolf2014-03-15
* Progress in Verific bindingsClifford Wolf2014-03-15
* Progress in Verific bindingsClifford Wolf2014-03-15
* Progress in Verific bindingsClifford Wolf2014-03-15
* Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() APIClifford Wolf2014-03-15
* Progress in Verific bindingsClifford Wolf2014-03-14
* Added log_dump() support for generic pointersClifford Wolf2014-03-14
* Progress in Verific bindingsClifford Wolf2014-03-14
* Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate APIClifford Wolf2014-03-14
* Progress in Verific bindingsClifford Wolf2014-03-13
* Copy Verific vdbs files to Yosys "share" data directoryClifford Wolf2014-03-13
* Small improvement in SAT log messagesClifford Wolf2014-03-13
* Added test_navre.ys for verific frontendClifford Wolf2014-03-13
* Hotfix for kernel/compatibility.hClifford Wolf2014-03-13
* Merge branch 'master' of https://github.com/Siesh1oo/yosysClifford Wolf2014-03-13
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| * - Makefile, kernel/posix_compatibility.h/.cc: replay isolated OSX/POSIX.2008...Siesh1oo2014-03-13
| * Merge branch 'master' of https://github.com/Siesh1oo/yosysSiesh1oo2014-03-13
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| | * - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_shar...Siesh1oo2014-03-12
| | * - Makefile: don't export DYLD_LIBRARY_PATH/LD_LIBRARY_PATH: not needed if we...Siesh1oo2014-03-12
| | * - .gitignore: ignore qmake/OSX package libs/svgviewer/svgviewer.appSiesh1oo2014-03-12
| | * - Makefile: follow changes in https://github.com/cliffordwolf/yosysSiesh1oo2014-03-12
| | * - libs/minisat/Solver.cc: insert spaces between string and PRIu64 literal, o...Siesh1oo2014-03-12
| | * - libs/minisat/System.cc: fix definition/declaration mismatch for Minisat::m...Siesh1oo2014-03-12
| | * Merge branch 'master' of https://github.com/Siesh1oo/yosysSiesh1oo2014-03-12
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| | | * - Makefile: don't add '-g' after '-ggdb' to CXXFLAGSSiesh1oo2014-03-11
| | | * Rebase to cliffordwolf repo HEAD finished.Siesh1oo2014-03-11
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| | | | * - passes/techmap/Makefile.inc: POSIX 'od' has no '-w' option. Use '-An' inst...Siesh1oo2014-03-11
| | | | * - Makefile: include $(PWD) in PATH, since 'make test' can happen before 'mak...Siesh1oo2014-03-10
| | | | * - libs/ezsat/ezminisat.cc: use sigemptyset() to clear sig_action.sa_mask; us...Siesh1oo2014-03-10
| | | | * - Makefile: fix typo in LDFLAGS: obviously -L, not -I is required hereSiesh1oo2014-03-10
| | | | * - Makefile: export PATH=${DESTDIR}/bin:$(PATH) and (DY)LD_LIBRARY_PATH, to m...Siesh1oo2014-03-10
| | | | * - frontends/vhdl2verilog/vhdl2verilog.cc, passes/abc/abc.cc: #include <climi...Siesh1oo2014-03-10