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* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-31
* Added "techmap -assert"Clifford Wolf2014-07-31
* Reorganized stdcells.v (no actual code change, just moved and indented stuff)Clifford Wolf2014-07-31
* Added "yosys -A"Clifford Wolf2014-07-31
* Added "yosys -Q"Clifford Wolf2014-07-31
* Added techmap CONSTMAP featureClifford Wolf2014-07-30
* Fixed counting verilog line numbers for "// synopsys translate_off" sectionsClifford Wolf2014-07-30
* Added write_file commandClifford Wolf2014-07-30
* Added "make -j{N}" support to "make test"Clifford Wolf2014-07-30
* Improvements in test_cellClifford Wolf2014-07-30
* New techmap default rules for $shr $sshr $shl $sshlClifford Wolf2014-07-30
* Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT modelsClifford Wolf2014-07-30
* Added native support for shift operations to ezSATClifford Wolf2014-07-30
* Added "log_dump_val_worker(char *v)"Clifford Wolf2014-07-30
* Added CodingStyle documentClifford Wolf2014-07-30
* Added "kernel/yosys.h" and "kernel/yosys.cc"Clifford Wolf2014-07-30
* Added "test_cell" commandClifford Wolf2014-07-29
* Renamed "write_autotest" to "test_autotb" and moved to passes/tests/Clifford Wolf2014-07-29
* Fixed Verilog pre-processor for files with no trailing newlineClifford Wolf2014-07-29
* Bugfix in simlib.v for iverilogClifford Wolf2014-07-29
* Allow "hierarchy -generate" for $__ cellsClifford Wolf2014-07-29
* Added "techmap -map %{design-name}"Clifford Wolf2014-07-29
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
* Removed left over debug codeClifford Wolf2014-07-28
* Fixed part selects of parametersClifford Wolf2014-07-28
* Set results of out-of-bounds static bit/part select to undefClifford Wolf2014-07-28
* Fixed RTLIL code generator for part select of parameterClifford Wolf2014-07-28
* Fixed width detection for part selectsClifford Wolf2014-07-28
* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-28
* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-28
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Added std::initializer_list<> constructor to SigSpecClifford Wolf2014-07-28
* Added cover() to all SigSpec constructorsClifford Wolf2014-07-28
* Fixed signdness detection of expressions with bit- and part-selectsClifford Wolf2014-07-28
* Improvements in tests/vloghtbClifford Wolf2014-07-28
* Added techmap -externClifford Wolf2014-07-27
* Added proper Design->addModule interfaceClifford Wolf2014-07-27
* Added topological sorting to techmapClifford Wolf2014-07-27
* Added SigPool::check(bit)Clifford Wolf2014-07-27
* Small improvements in PerformanceTimer APIClifford Wolf2014-07-27
* Fixed bug in opt_cleanClifford Wolf2014-07-27
* Improved performance of opt_const on large modulesClifford Wolf2014-07-27
* Added RTLIL::SigSpec::remove_const() handling of packed SigSpecsClifford Wolf2014-07-27
* Added RTLIL::SigSpecConstIteratorClifford Wolf2014-07-27
* Fixed a bug in opt_clean and some RTLIL API usage cleanupsClifford Wolf2014-07-27
* Added log_cmd_error_expectionClifford Wolf2014-07-27
* Fixed verific bindings for new RTLIL apiClifford Wolf2014-07-27
* Fixed ilang parser for new RTLIL APIClifford Wolf2014-07-27
* Using new obj iterator API in a few placesClifford Wolf2014-07-27
* Added RTLIL::Module::wire(id) and cell(id) lookup functionsClifford Wolf2014-07-27