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*
Added RTLIL::Design::modules()
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
*
Added conversion from ObjRange to std::vector and std::set
Clifford Wolf
2014-07-27
*
Added RTLIL::ObjIterator and RTLIL::ObjRange
Clifford Wolf
2014-07-27
*
Using std::move() in SigSpec move constructor
Clifford Wolf
2014-07-27
*
Added RTLIL::SigSpec move constructor and move assignment operator
Clifford Wolf
2014-07-27
*
Mostly cosmetic changes to rtlil.h
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
*
New message for completion of build
Clifford Wolf
2014-07-26
*
Changed more code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
*
Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
*
Added tests/various/.gitignore
Clifford Wolf
2014-07-26
*
Added tests/various/submod_extract.ys
Clifford Wolf
2014-07-26
*
Added support for here documents
Clifford Wolf
2014-07-26
*
More RTLIL::Cell API usage cleanups
Clifford Wolf
2014-07-26
*
Added RTLIL::Cell::has(portname)
Clifford Wolf
2014-07-26
*
Merge automatic and manual code changes for new cell connections API
Clifford Wolf
2014-07-26
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*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
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*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
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/
*
Added some missing "const" in rtlil.h
Clifford Wolf
2014-07-26
*
Added RTLIL::Module::connections()
Clifford Wolf
2014-07-26
*
Added RTLIL::Module::connect(const RTLIL::SigSig&)
Clifford Wolf
2014-07-26
*
Use "wget -N" in tests/vloghtb/run-test.sh
Clifford Wolf
2014-07-26
*
Added "passed" message to make test targets
Clifford Wolf
2014-07-26
*
Automatically pack SigSpec on copy/assign
Clifford Wolf
2014-07-26
*
Added new RTLIL::Cell port access methods
Clifford Wolf
2014-07-26
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
*
Cosmetic fixes for "make abc"
Clifford Wolf
2014-07-26
*
Added "Checklist for adding internal cell types"
Clifford Wolf
2014-07-26
*
Added copy-constructor-like module->addCell(name, other) method
Clifford Wolf
2014-07-26
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
*
Various RTLIL::SigSpec related code cleanups
Clifford Wolf
2014-07-25
*
Added RTLIL::SigSpec is_chunk()/as_chunk() API
Clifford Wolf
2014-07-25
*
Added "make vgtest"
Clifford Wolf
2014-07-25
*
Fixed two memory leaks in ast simplify
Clifford Wolf
2014-07-25
*
Renamed some of the test cases in tests/simple to avoid name collisions
Clifford Wolf
2014-07-25
*
Fixed memory corruption in "opt_reduce" pass
Clifford Wolf
2014-07-25
*
Disabled cover() for non-linux builds
Clifford Wolf
2014-07-25
*
Added more stuff to checklist
Clifford Wolf
2014-07-25
*
Updated verific build/test instructions
Clifford Wolf
2014-07-25
*
Improvements in "cover" command
Clifford Wolf
2014-07-25
*
Removed Minisat dependency on zlib
Clifford Wolf
2014-07-25
*
Added more stuff to the checklist
Clifford Wolf
2014-07-25
*
Fixed typo in cover id
Clifford Wolf
2014-07-25
*
Added "make clean-abc"
Clifford Wolf
2014-07-25
*
Further improved "make" prettiness
Clifford Wolf
2014-07-25
*
Replaced more old SigChunk programming patterns
Clifford Wolf
2014-07-24
*
Updated ABC to hg id "b1e63d18768d"
Clifford Wolf
2014-07-24
*
Added cover() calls to opt_const
Clifford Wolf
2014-07-24
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