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* Added test_verific mode to tests/fsm/generate.pyClifford Wolf2014-08-12
* Fixed SigBit(RTLIL::Wire *wire) constructorClifford Wolf2014-08-12
* Fixed building verific bindingsClifford Wolf2014-08-12
* Added multi-dim memory test (requires iverilog git head)Clifford Wolf2014-08-12
* Another build fix by americanrouter (via reddit)Clifford Wolf2014-08-11
* Fixed FSM mapping for multiple reset-like signalsClifford Wolf2014-08-10
* Fixed "share" for complex scenarios with never-active cellsClifford Wolf2014-08-09
* Do not share any $reduce_* cells (its complicated and not worth it anyways)Clifford Wolf2014-08-09
* Some improvements in fsm_opt and fsm_map for FSM with unreachable statesClifford Wolf2014-08-09
* Improved FSM testsClifford Wolf2014-08-08
* Another fsm_extract bugfixClifford Wolf2014-08-08
* Fixed "fsm -export"Clifford Wolf2014-08-08
* Fixed sharing of reduce operatorClifford Wolf2014-08-08
* Fixed fsm_extract for wreduced muxesClifford Wolf2014-08-08
* Added FSM test benchClifford Wolf2014-08-08
* Added "sat -prove-skip"Clifford Wolf2014-08-08
* Fixed build with gcc-4.6Clifford Wolf2014-08-07
* Use "-keepdc" in "miter -equiv -flatten"Clifford Wolf2014-08-07
* Also allow "module foobar(input foo, output bar, ...);" syntaxClifford Wolf2014-08-07
* Added adff2dff.v (for techmap -share_map)Clifford Wolf2014-08-07
* Added AST_MULTIRANGE (arrays with more than 1 dimension)Clifford Wolf2014-08-06
* Various improvements in memory_dff passClifford Wolf2014-08-06
* Various fixes and improvements in wreduce passClifford Wolf2014-08-05
* Removed old "constmap" from wreduce codeClifford Wolf2014-08-05
* Added support for truncating of wires to wreduce passClifford Wolf2014-08-05
* Cleanups and improvements in wreduce passClifford Wolf2014-08-05
* Added mux support to wreduce commandClifford Wolf2014-08-05
* Improved scope resolution of local regs in Verilog+AST frontendClifford Wolf2014-08-05
* Fixed AST handling of variables declared inside a functions main blockClifford Wolf2014-08-05
* Added "show -signed"Clifford Wolf2014-08-04
* Added support for non-standard "module mod_name(...);" syntaxClifford Wolf2014-08-04
* Added RTLIL::IdString::in(...)Clifford Wolf2014-08-04
* Fixed "share" for memory read portsClifford Wolf2014-08-03
* Added "wreduce" to some of the standard test benchesClifford Wolf2014-08-03
* Progress in "wreduce" passClifford Wolf2014-08-03
* Added "wreduce" command (work in progress)Clifford Wolf2014-08-03
* Added query() API to ModIndexClifford Wolf2014-08-03
* Added ID() macro for static IdStringsClifford Wolf2014-08-03
* Implemented recursive techmapClifford Wolf2014-08-03
* Fixes in show command (related to new IdString)Clifford Wolf2014-08-03
* Implemented simplemap support for "techmap -extern"Clifford Wolf2014-08-02
* Fixed a va_list corruption in logv_error()Clifford Wolf2014-08-02
* Be more conservative with printing decimal numbers in verilog backendClifford Wolf2014-08-02
* Improved verilog output for ordinary $mux cellsClifford Wolf2014-08-02
* Bugfix in "techmap -extern"Clifford Wolf2014-08-02
* Removed at() method from RTLIL::IdStringClifford Wolf2014-08-02
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-02
* Limit size of log_signal buffer to 100 elementsClifford Wolf2014-08-02
* Improvements in new RTLIL::IdString implementationClifford Wolf2014-08-02