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* Added note about SystemVerilog assert statement to READMEClifford Wolf2014-02-01
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* Added miter commandClifford Wolf2014-02-01
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* Progress on presentationClifford Wolf2014-01-31
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* More changes to techlibs/common/simlib.v for LECClifford Wolf2014-01-31
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* presentation progressClifford Wolf2014-01-30
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* Bugfix in name resolution with generate blocksClifford Wolf2014-01-30
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* Added yosys -H for command listClifford Wolf2014-01-30
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* presentation progressClifford Wolf2014-01-29
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* presentation progressClifford Wolf2014-01-29
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* Tiny change in example script in READMEClifford Wolf2014-01-29
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* Added -h command line optionClifford Wolf2014-01-29
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* Added test comments to techlibs/cmos/cmos_cells.libClifford Wolf2014-01-29
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* Updated ABC to hg rev e6b09e1Clifford Wolf2014-01-29
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* Added read_verilog -icells optionClifford Wolf2014-01-29
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* Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)Clifford Wolf2014-01-29
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* presentation progressClifford Wolf2014-01-28
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* Renamed manual/FILES_* directoriesClifford Wolf2014-01-28
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* Progress on presentationClifford Wolf2014-01-28
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* Progress on presentationClifford Wolf2014-01-27
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* Added first presentation slidesClifford Wolf2014-01-27
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* Merge branch 'btor' of https://github.com/ahmedirfan1983/yosysClifford Wolf2014-01-26
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| * root bug correctedAhmed Irfan2014-01-25
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* | Merge pull request #21 from hansiglaser/masterClifford Wolf2014-01-25
|\ \ | | | | | | beautified write_intersynth, enabled multiple "-map" for the extract pass
| * | enabled multiple "-map" for the extract passJohann Glaser2014-01-25
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| * | beautified write_intersynthJohann Glaser2014-01-25
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* | Added support for // comments in liberty parserClifford Wolf2014-01-25
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* | Merge branch 'btor'Clifford Wolf2014-01-24
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| * removed regex includeAhmed Irfan2014-01-24
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| * merged clifford changes + removed regexAhmed Irfan2014-01-24
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| * Use techmap -share_map in btor scriptsClifford Wolf2014-01-24
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| * Moved btor scripts to backends/btor/Clifford Wolf2014-01-24
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| * Restored MakefileClifford Wolf2014-01-24
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| * Restored IdString::check()Clifford Wolf2014-01-24
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| * Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys into btorClifford Wolf2014-01-24
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| * minor change in scriptAhmed Irfan2014-01-24
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| * Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-01-22
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| * | slice bug correctedAhmed Irfan2014-01-20
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| * | assert featureAhmed Irfan2014-01-20
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| * | Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-01-20
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| * | | script addedAhmed Irfan2014-01-18
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| * | | Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-18
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| | * \ \ Merge branch 'master' of https://github.com/ahmedirfan1983/yosysAhmed Irfan2014-01-18
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| | * \ \ \ Merge branch 'master' of https://github.com/cliffordwolf/yosysAhmed Irfan2014-01-18
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| * | \ \ \ \ pmux2muxAhmed Irfan2014-01-18
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| * | | | | | verilog default options pullAhmed Irfan2014-01-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | shift operator width issues
| * | | | | | Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-17
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| | * | | | | Merge pull request #4 from cliffordwolf/masterAhmed Irfan2014-01-17
| | |\ \ \ \ \ | | | | | | | | | | | | | | | | verilog defaults
| * | \ \ \ \ \ Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btorAhmed Irfan2014-01-17
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| | * | | | | | Merge pull request #3 from cliffordwolf/masterAhmed Irfan2014-01-17
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| * | | | | | | slice error correctedAhmed Irfan2014-01-16
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